Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

Patent metadata

Field	Value
Publication number	US-10790814-B2
Application number	US-201916671967-A
Country	US
Kind code	B2
Filing date	Nov 1, 2019
Priority date	Jul 11, 2005
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

First claim

What is claimed is:

1. A method of operating at least one integrated circuit chip, the method comprising:
inputting an input RF signal and one or more control signals to the at least one integrated circuit chip;
outputting an output RF signal from the at least one integrated circuit chip;
controlling, based at least in part on the one or more control signals, a silicon on insulator (SOI) N-type metal oxide semiconductor (NMOS) field effect transistor (FET) series connected stack configuration to either an OFF state or an ON state, the SOI NMOS FET stack configuration, comprising a plurality of NMOS FET transistors, being implemented in the at least one integrated circuit chip; and
electrically biasing, based at least in part on the one or more control signals, a body of at least one NMOS FET transistor of the plurality of NMOS FET transistors of the SOI NMOS FET stack configuration with a bias voltage substantially more negative than ground during at least a portion of the OFF state of the at least one NMOS FET transistor.

2. The method of claim 1 , wherein the method further comprises generating the bias voltage substantially more negative than ground in the at least one integrated circuit chip.

3. The method of claim 1 , and further comprising:
removing or otherwise controlling charge that has and/or had accumulated in the body of the at least one NMOS FET transistor.

4. The method of claim 1 , wherein the electrically biasing the body of the at least one NMOS FET transistor during the at least a portion of the OFF state comprises at least improving linearity of the at least one NMOS FET transistor.

5. The method of claim 1 , wherein the electrically biasing the body of the at least one NMOS FET transistor during the at least a portion of the OFF state comprises reducing distortion of the output RF signal.

6. The method of claim 5 , wherein the reducing the distortion of the output RF signal comprises reducing harmonic distortion of the output RF signal.

7. The method of claim 1 , wherein the controlling of the SOI NMOS FET stack configuration comprises controlling a plurality of gates of the plurality of NMOS FET transistors in which respective NMOS FET transistors thereof have a respective gate coupled to a respective resistor.

8. The method of claim 1 , wherein the electrically biasing the body of the at least one NMOS FET transistor of the plurality of NMOS FET transistors comprises electrically biasing a plurality of bodies of the plurality of NMOS FET transistors on the at least one integrated circuit chip, the at least one integrated circuit chip comprising a silicon on insulator (SOI) substrate including a thin film silicon layer with a thickness less than 150 nm.

9. The method of claim 1 , wherein the electrically biasing the body of the at least one NMOS FET transistor of the plurality of NMOS FET transistors comprises electrically biasing a plurality of bodies of the plurality of NMOS FET transistors in the at least one integrated circuit chip, the at least one integrated circuit chip comprising a silicon on insulator (SOI) substrate including a thin film silicon layer on an insulating layer with respective sources and drains of respective NMOS FET transistors of the plurality extending through the entire thickness of the thin film silicon layer to the insulating layer.

10. The method of claim 1 , and further comprising:
during the at least a portion of the OFF state of the SOI NMOS FET stack configuration, in which the SOI NMOS FET stack configuration is operating in an RF switch, not passing an RF signal through the RF switch, wherein the RF switch is within the at least one integrated circuit chip; and
during at least a portion of the ON state of the SOI NMOS FET stack configuration, in which the SOI NMOS FET stack configuration is operating in an RF switch, passing the RF signal through the RF switch, wherein the RF switch is within the at least one integrated circuit chip.

11. The method of claim 10 , wherein the not passing the RF signal through the RF switch comprises not passing a high-power RF signal through the RF switch; and
wherein the passing the RF signal through the RF switch comprises passing the high-power RF signal through the RF switch.

12. The method of claim 10 , wherein the not passing the RF signal through the RF switch comprises not passing a GSM compliant RF signal through the RF switch; and
wherein the passing the RF signal through the RF switch comprises passing the GSM compliant RF signal through the RF switch.

13. The method of claim 1 , and further comprising:
not shunting an RF port to ground during the at least a portion of the OFF state of the SOI NMOS FET stack configuration; and
shunting the RF port to ground during at least a portion of the ON state of the SOI NMOS FET stack configuration.

14. The method of claim 1 , and further comprising:
not passing an RF signal during the at least a portion of the OFF state of the SOI NMOS FET stack configuration; and
passing the RF signal during at least a portion of the ON state of the SOI NMOS FET stack configuration.

15. The method of claim 14 , wherein the passing the RF signal and the not passing the RF signal comprises passing the RF signal and not passing the RF signal taking place in the at least one integrated circuit chip, in addition to the controlling and the electrical biasing, during use of the at least one integrated circuit chip in a cellular wireless communication system.

16. A method of operating a thin film silicon on insulator (SOI)N-type metal oxide semiconductor (NMOS) field effect transistor (FET), the method comprising:
controlling the thin film SOI NMOS FET transistor to an OFF state; and
electrically biasing a body of the thin film SOI NMOS FET transistor with a bias voltage substantially more negative than ground during at least a portion of the OFF state of the thin film SOI NMOS FET transistor.

17. The method of claim 16 , and further comprising:
providing a bias voltage substantially more negative than ground to electrically bias the body of the thin film SOI NMOS FET transistor.

18. The method of claim 16 , and further comprising:
removing or otherwise controlling charge that has and/or had accumulated in the body of the thin film SOI NMOS FET transistor.

19. The method of claim 16 , wherein the electrically biasing the body of the thin film SOI NMOS FET transistor during the at least a portion of the OFF state comprises at least improving linearity of the thin film SOI NMOS FET transistor.

20. The method of claim 16 , wherein the thin film SOI NMOS FET transistor is coupled between two nodes, the electrically biasing the body of the thin film SOI NMOS FET transistor during the at least a portion of the OFF state of the thin film SOI NMOS FET transistor comprises reducing distortion of an electrical signal passing through one of the two nodes.

21. The method of claim 20 , wherein the thin film SOI NMOS FET transistor is coupled as a pass thin film SOI NMOS FET transistor between the two nodes, and wherein the reducing distortion of the electrical signal passing through the one of the two nodes comprises reducing harmonic distortion of the electrical signal.

22. The method of claim 20 , wherein the thin film SOI NMOS FET transistor is coupled as a shunt thin film SOI NMOS FET transistor between one node and ground, and wherein the reducing distortion of the electrical signal passing through the one node comprises reducing harmonic distortion of

Assignees

• Psemi Corp

Inventors

• Brindle Christopher N
• Stuber Michael A
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George
• Welstand Robert B
• Burgener Mark L

Classifications

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title

• H10D30/675

  Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/6711

  by using electrodes contacting the supplementary regions or layers · CPC title