Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction

Patent metadata

Field	Value
Publication number	US-10790390-B2
Application number	US-201916377026-A
Country	US
Kind code	B2
Filing date	Apr 5, 2019
Priority date	Jul 11, 2005
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

First claim

The invention claimed is:

1. An RF module comprising: at least one integrated circuit chip;
the at least one integrated circuit chip included in the RF module and further including at least one field effect transistor, the at least one field effect transistor including a gate, a drain, a source, and a body;
wherein, during at least a portion of an off state, the body of the at least one field effect transistor is to be electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor;
wherein the body of the at least one field effect transistor is electrically coupled to at least two accumulated charge sinks; and
wherein the at least two accumulated charge sinks are coupled through a path having low impedance.

2. The RF module of claim 1 , wherein the at least one field effect transistor comprises an N-type metal oxide semiconductor (NMOS) field effect transistor.

3. The RF module of claim 1 , wherein the at least one field effect transistor is implemented in a silicon on insulator technology.

4. The RF module of claim 1 , wherein the voltage level substantially more negative than the lowest voltage level is more than one volt more negative than the lowest voltage level.

5. The RF module of claim 1 , wherein, the body of the at least one field effect transistor is electrically coupled to the at least two accumulated charge sinks so as to remove or otherwise control, via the at least two accumulated charge sinks, charge that, without the body being electrically biased, would accumulate in the body of the at least one field effect transistor.

6. The RF module of claim 1 , wherein the at least one field effect transistor during the at least a portion of the off state is to be electrically biased so as to improve the linearity of the at least one field effect transistor relative to the at least one field effect transistor not electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor.

7. The RF module of claim 1 , wherein the at least one field effect transistor during the at least a portion of the off state is to be electrically biased so as to reduce non-linear harmonic and/or intermodulation distortion of RF signals to be propagated by the RF module, reduction via the at least one field effect transistor being relative to the at least one field effect transistor not electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor.

8. The RF module of claim 7 , wherein the power of a third harmonic of the RF signals to be propagated via the RF module is to be lower than −30dBm at an operating power of +35dBm power.

9. The RF module of claim 1 , wherein the at least one field effect transistor is included in a stack of field effect transistors included in an RF switch, the RF switch being included in the at least one integrated circuit chip.

10. The RF module of claim 1 , wherein the at least two accumulated charge sinks comprise more than two accumulated charge sinks and wherein the more than two accumulated charge sinks are coupled through paths having low impedance.

11. A communication device comprising: at least one integrated circuit chip;
the at least one integrated circuit chip included in the communication device and further including an RF switch comprising at least one field effect transistor, the at least one field effect transistor including a gate, a drain, a source, and a body;
wherein, during at least a portion of an off state, the body of the at least one field effect transistor is to be electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor;
wherein the body of the at least one field effect transistor is electrically coupled to at least two accumulated charge sinks; and
wherein the at least two accumulated charge sinks are coupled through a path having low impedance.

12. The communication device of claim 11 , wherein the at least one field effect transistor comprises an N-type metal oxide semiconductor (NMOS) field effect transistor.

13. The communication device of claim 11 , wherein the at least one field effect transistor is implemented in a silicon on insulator technology.

14. The communication device of claim 11 , wherein the voltage level substantially more negative than the lowest voltage level is more than one volt more negative than the lowest voltage level.

15. The communication device of claim 11 , wherein the body of the at least one field effect transistor is electrically coupled to the at least two accumulated charge sinks so as to remove or otherwise control, via the at least two accumulated charge sinks, charge that, without the body being electrically biased, would accumulate in the body of the at least one field effect transistor.

16. The communication device of claim 11 , wherein the at least one field effect transistor during the at least a portion of the off state is to be electrically biased so as to improve the linearity of the at least one field effect transistor relative to the at least one field effect transistor not electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor.

17. The communication device of claim 11 , wherein the at least one field effect transistor during the at least a portion of the off state is to be electrically biased so as to reduce non-linear harmonic and/or intermodulation distortion of RF signals to be propagated by the communication device, reduction via the at least one field effect transistor being relative to the at least one field effect transistor not electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one field effect transistor, and the DC voltage level of the drain of the at least one field effect transistor.

18. The communication device of claim 17 , wherein the power of a third harmonic of the RF signals to be propagated via the RF switch is to be lower than—30dBm at an operating power of +35dBm power.

19. The communication device of claim 11 , wherein the at least one field effect transistor is included in a stack of field effect transistors included in an RF switch, the RF switch being included in the at least one integrated circuit chip.

20. The communication device of claim 11 , wherein the at least two accumulated charge sinks comprise more than two accumulated charge sinks and wherein the more than two accumulated charge sinks are coupled through paths having low impedance.

21.

Assignees

• Psemi Corp

Inventors

• Brindle Christopher N
• Deng Jie
• Genc Alper
• Yang Chieh-Kai

Classifications

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/378

  Contact regions to the substrate regions · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/125

  Shapes of junctions between the regions · CPC title