Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

Patent metadata

Field	Value
Publication number	US-10790815-B2
Application number	US-201916673411-A
Country	US
Kind code	B2
Filing date	Nov 4, 2019
Priority date	Jul 11, 2005
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

First claim

What is claimed is:

1. A device comprising: at least one integrated circuit chip; the at least one integrated circuit chip including a plurality of N-type metal oxide semiconductor field effect transistors (NMOSFETs) arranged in a series connected stack configuration;
wherein at least one NMOSFET transistor of the plurality includes a source, a gate, a drain and a body;
wherein the at least one NMOSFET transistor is further included in an electrical configuration within the at least one integrated circuit chip, the electrical configuration to at least control the at least one NMOSFET transistor to either an ON state or an OFF state based at least on one or more control signals; and wherein the electrical configuration is at least further to electrically bias the body of the at least one NMOSFET transistor to a DC voltage level substantially more negative than ground at least in a portion of the OFF state of the at least one NMOSFET transistor.

2. The device of claim 1 , wherein the electrical configuration, at least in the portion of the OFF state of the at least one NMOSFET transistor, is at least to remove or otherwise control charge that, without the body of the at least one NMOSFET transistor being electrically biased to the DC voltage level substantially more negative than ground, would accumulate and/or would have accumulated in the body of the at least one NMOSFET transistor.

3. The device of claim 1 , wherein the electrical configuration is at least further to electrically bias the body of the at least one NMOSFET transistor to the DC voltage level substantially more negative than ground at least to improve linearity of the at least one NMOSFET transistor relative to an electrical configuration without the body of the at least one NMOSFET transistor being electrically biased to the DC voltage level substantially more negative than ground.

4. The device of claim 1 , wherein the at least one integrated circuit chip comprises a silicon on insulator (SOI) substrate.

5. The device of claim 4 , wherein the SOI substrate includes at least a thin film silicon layer with a thickness less than 150 nm.

6. The device of claim 4 , wherein the SOI substrate includes at least a thin film silicon layer on an insulating layer wherein the source and the drain of the at least one NMOSFET extend through the thin film silicon layer to the insulating layer.

7. The device of claim 1 , wherein the at least one integrated circuit chip further comprises a negative voltage generator circuit to generate the DC voltage level substantially more negative than ground at least to electrically bias the body of the at least one NMOSFET transistor at least in the portion of the OFF state.

8. The device of claim 7 , wherein the negative voltage generator circuit comprises a charge pump.

9. The device of claim 1 , wherein the DC voltage level substantially more negative than ground comprises a DC voltage level at least one volt more negative than ground.

10. The device of claim 1 , wherein the electrical configuration is at least to control other NMOSFET transistors of the stack to the OFF state and at least to electrically bias the other NMOSFET transistors to the DC voltage level substantially more negative than ground at least in the portion of the OFF state.

11. The device of claim 10 , wherein the stack comprises a switch NMOSFET transistor stack.

12. The device of claim 10 , wherein the stack comprises a shunt NMOSFET transistor stack.

13. The device of claim 10 , wherein the stack configuration is included in an RF switch within the at least one integrated circuit chip.

14. The device of claim 1 , wherein the electrical configuration is at least further to electrically bias the body of the at least one NMOSFET transistor to the DC voltage level substantially more negative than ground at least to reduce distortion of the at least one NMOSFET transistor relative to an electrical configuration without the body of the at least one NMOSFET transistor being electrically biased to the DC voltage level substantially more negative than ground.

15. The device of claim 1 , wherein the at least one integrated circuit is included in an RF module.

16. The device of claim 15 , wherein the RF module is operable at least for use in a cellular communication system.

17. The device of claim 16 wherein the RF module comprises an RF module operable at least for use in an at least GSM cellular communication system.

18. The device of claim 1 , and further comprising at least one accumulated charge sink (ACS) coupled to the body of the at least one NMOSFET transistor.

19. A device comprising: at least one N-type metal oxide semiconductor field effect transistor (NMOSFET), the at least one NMOSFET transistor including a source, a gate, a drain and a body;
wherein the at least one NMOSFET transistor comprises a thin film silicon on insulator (SOI) NMOSFET transistor;
wherein the at least one thin film SOI NMOSFET transistor is further included in an electrical configuration at least to control the at least one thin film SOI NMOSFET transistor to an OFF state;
wherein the electrical configuration is at least further to electrically bias the body of the at least one thin film SOI NMOSFET transistor to a DC voltage level substantially more negative than ground at least in a portion of the OFF state of the at least one thin film SOI NMOSFET transistor.

20. The device of claim 19 , wherein a thin film SOI substrate of the thin film SOI NMOSFET transistor comprises at least a thin film silicon layer with a thickness less than 150 nm.

21. The device of claim 19 , wherein the thin film SOI substrate of the thin film SOI NMOSFET transistor comprises at least a thin film silicon layer on an insulating layer wherein the source and the drain of the at least one thin film SOI NMOSFET transistor extend through the thin film silicon layer to the insulating layer.

22. The device of claim 19 , wherein the DC voltage level substantially more negative than ground comprises a DC voltage level at least one volt more negative than ground.

23. The device of claim 19 , wherein the electrical configuration, at least in the portion of the OFF state of the at least one thin film SOI NMOSFET transistor, is at least to remove or otherwise control charge that, without the body of the at least one thin film SOI NMOSFET being electrically biased to the DC voltage level substantially more negative than ground, would accumulate and/or would have accumulated in the body of the at least one thin film SOI NMOSFET transistor.

24. The device of claim 19 , wherein the electrical configuration is at least further to electrically bias the body of the at least one thin film SOI NMOSFET transistor to the DC voltage level substantially more negative than ground at least to improve linearity of the at least one thin film SOI NMOSFET transistor relative to an electrical configuration without the body of the at least one thin film SOI NMOSFET transistor being electrically biased to the DC voltage level substantially more negative than ground.

25. The device of claim 19 , wherein the electrical configuration is at least further to electrically bias the body of the at least one thin film SOI NMOSFET transistor to the DC voltage level substantially more negative than ground at least to reduce distortion of the at least one thin film SOI NMOSFET transistor relative to an electrical configuration without the body of the at least

Assignees

• Psemi Corp

Inventors

• Brindle Christopher N
• Stuber Michael A
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George
• Welstand Robert B
• Burgener Mark L

Classifications

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title

• H10D30/675

  Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/6711

  by using electrodes contacting the supplementary regions or layers · CPC title