Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction

Patent metadata

Field	Value
Publication number	US-10797172-B2
Application number	US-201816046974-A
Country	US
Kind code	B2
Filing date	Jul 26, 2018
Priority date	Jul 11, 2005
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

First claim

The invention claimed is:

1. An RF switch circuit for switching RF signals, comprising:
(A) a first RF port;
(B) a second RF port; and
(C) a pass transistor grouping having a first node coupled to the first RF port and a second node coupled to the second RF port, the pass transistor grouping comprising a first two or more accumulated charge control N-type MOSFETs (ACC N-MOSFETs) arranged in a stacked configuration; and
wherein:
(a) each ACC N-MOSFET of the first two or more ACC N-MOSFETs comprises:
(i) a first gate, a first drain, a first source, a first gate oxide layer, and a first body, wherein the first gate oxide layer is positioned between the first gate and the first body; and
(ii) two or more first accumulated charge sink (ACS) regions positioned proximate to portions of the first body, wherein each first ACS region of the two or more ACS regions is connected to the first body;

(b) the pass transistor grouping configured to couple the first RF port with the second RF port in a pass transistor grouping first state;
(c) the pass transistor grouping configured to isolate the first RF port from the second RF port in a pass transistor grouping second state, and wherein the pass transistor grouping is configured to have first bias voltages applied to the two or more ACS regions to remove or otherwise control, via the two or more first ACS regions, charge that, without the first bias voltages applied, would accumulate in the first body in the pass transistor grouping second state; and
(d) the first bias voltages being substantially negative with respect to ground, the first drain and the first source.

2. The RF switch circuit of claim 1 , further comprising a shunt transistor grouping having a first node coupled to the first RF port and a second node coupled to ground, and the shunt transistor grouping comprising a second two or more ACC N-MOSFETs arranged in a stacked configuration,
wherein:
(a′) each ACC N-MOSFET of the second two or more ACC N-MOSFETs comprises:
(i′) a second gate, a second drain, a second source, a second body and a second gate oxide layer, wherein the second gate oxide layer is positioned between the second gate and the second body; and
(ii′) two or more second accumulated charge sink (ACS) regions positioned proximate to portions of the second body, and wherein each second ACS region of the two or more ACS regions is connected to the second body;

(b′) the shunt transistor grouping configured to shunt the first RF port with the first RF port being coupled to ground in a shunt transistor grouping first state;
(c′) the shunt transistor grouping configured to isolate the first RF port from ground in a shunt transistor grouping second state, and wherein the shunt transistor grouping is configured to have second bias voltages applied to the two or more second ACS regions to remove or otherwise control, via the two or more second ACS regions, charge that, without the second bias voltages applied, would accumulate in the second body in the shunt transistor grouping second state; and
(d′) the second bias voltages being substantially negative with respect to ground, the second drain and the second source.

3. The RF switch circuit of claim 2 , wherein:
the pass transistor grouping is controllable by a first switch control signal; and
the shunt transistor grouping is controllable by a second switch control signal.

4. The RF switch circuit of claim 3 , wherein:
the pass transistor grouping is enabled in the pass transistor grouping first state by the first switch control signal to couple the first RF port with the second RF port and the shunt transistor grouping is disabled in the shunt transistor grouping second state by the second switch control signal to isolate the first RF port from ground; and
the shunt transistor grouping is enabled in the shunt transistor grouping first state by the second switch control signal to shunt the first RF port to ground with the first RF port being coupled to ground and the pass transistor grouping is disabled in the pass transistor grouping second state by the first switch control signal to isolate the first RF port from the second RF port.

5. The RF switch circuit of claim 4 , wherein the first two or more ACC N-MOSFETs arranged in the stacked configuration include respective gate resistors coupled to respective gates of the first two or more ACC N-MOSFETs, and wherein the second two or more ACC N-MOSFETs arranged in the stacked configuration include respective gate resistors coupled to respective gates of the second two or more ACC N-MOSFETs.

6. The RF switch circuit of claim 4 , wherein the RF circuit is incorporated in a cellular communication device.

7. The RF switch circuit of claim 6 , wherein the cellular communication device includes a GSM mode of operation.

8. The RF switch circuit of claim 6 , wherein the cellular communication device is capable of transmitting in a cellular communication system at a level below -30 dBm for one or more harmonics of a fundamental frequency.

9. The RF switch circuit of claim 2 , wherein the first two or more ACC N-MOSFETs and the second two or more ACC N-MOSFETs respectively include a thin-film semiconductor layer in a silicon on insulator (SOI) substrate.

10. The RF switch circuit of claim 5 , wherein the RF switch circuit is included on a single die.

11. A single-pole, multiple-throw RF switch comprising:
a plurality of pass transistor groupings i, i=1, 2, . . . N, with i being two or greater;
a plurality of corresponding first RF ports i, i=1, 2, . . . N, with i being two or greater;
a second RF port;
wherein:
two or more pass transistor groupings of the plurality of pass transistor groupings to respectively couple two or more corresponding first RF ports with the second RF port;
the plurality of pass transistor groupings respectively comprises first two or more ACC N-MOSFETs arranged in a stacked configuration;
each ACC N-MOSFET of respective first two or more ACC N-MOSFETs comprises a first body, a first gate, a first drain, a first source and a first gate oxide layer, wherein the first gate oxide layer is positioned between the first gate and the first body, and two or more accumulated charge sink (ACS) regions are positioned proximate to portions of the first body, and wherein each first ACS region of the two or more ACS regions is connected to the first body;
one of the two or more pass transistor groupings, i, configured to couple one corresponding first RF port, i, with the second RF port in a pass transistor grouping first state;
other of the two or more pass transistor groupings, other than the one of the two or more pass transistor groupings, i, configured to isolate the two or more corresponding first RF ports, other than the one corresponding first RF port, i, from the second RF port, in a pass transistor grouping second state, and wherein the other pass transistor groupings of the two or more pass transistor groupings, other than the one of the two or more pass transistor groupings, i, are configured to have first bias voltages applied to the two or more first ACS regions to remove or otherwise control, via the two or more first ACS regions, charge that, without the first bias voltages applied, would accumulate in the first body in the pass transistor grouping second state;
the first bias voltages being substantially negative with respect to ground, the first drain and the first source.

12. The single-pole, multiple-throw RF switch of claim 11 , wherein:
(a) for the one of the two or more pass transistor groupings, i, in the pass transistor grouping first state; and
(b) for the other pass transistor groupings, other than the one of

Assignees

• Psemi Corp

Inventors

• Brindle Christopher N
• Deng Jie
• Genc Alper
• Yang Chieh-Kai
• Stuber Michael A
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George
• Burgener Mark L
• Welstand Robert B

Classifications

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/378

  Contact regions to the substrate regions · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/125

  Shapes of junctions between the regions · CPC title