Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory

Patent metadata

Field	Value
Publication number	US-11901360-B2
Application number	US-202117456225-A
Country	US
Kind code	B2
Filing date	Nov 23, 2021
Priority date	Sep 5, 2018
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

In a method of forming a semiconductor device, a plurality of transistor pairs is formed to be stacked over a substrate. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. A sequence of vertical and lateral etch steps are performed to etch the plurality of the gate electrodes and the plurality of S/D local interconnects so that the plurality of the gate electrodes and the plurality of S/D local interconnects have a staircase configuration.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
forming a plurality of transistor pairs that are stacked over a substrate, wherein the plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs, wherein each of the plurality of transistor pairs comprises a n-type transistor and a p-type transistor that are stacked over one another; and
performing a sequence of vertical and lateral etch steps to etch the plurality of the gate electrodes and the plurality of S/D local interconnects so that the plurality of the gate electrodes and the plurality of S/D local interconnects have a staircase configuration.

2. The method of claim 1 , wherein the n-type transistor is positioned over the p-type transistor so as to form a complementary field effect transistor device.

3. The method of claim 1 , wherein the p-type transistor is positioned over the n-type transistor so as to form a complementary field effect transistor device.

4. The method of claim 1 , further comprising:
forming an array of vertical contacts that are positioned over the plurality of transistor pairs, arranged in a vertical direction perpendicular to the substrate and electrically coupled to the plurality of gate electrodes, and the plurality of S/D local interconnects.

5. The method of claim 1 , further comprising:
forming a series of wiring levels that are positioned over an array of vertical contacts and provide a functionality of the semiconductor device by connecting the array of vertical contacts.

6. The method of claim 1 , wherein the n-type transistor and the p-type transistor share a gate structure that is electrically coupled to one of the plurality of gate electrodes.

7. The method of claim 6 , wherein the plurality of S/D local interconnects extend in a horizontal direction parallel to the substrate with the staircase configuration.

8. The method of claim 7 , wherein the n-type transistor has a source region and a drain region that are positioned at two ends of a n-type channel region that is surrounded by the gate structure, the n-type channel region, the source region and the drain region of the n-type transistor being arranged in the horizontal direction.

9. The method of claim 7 , wherein the p-type transistor has a source region and a drain region that are positioned at two ends of a p-type channel region that is surrounded by the gate structure, the p-type channel region, the source region and the drain region of the p-type transistor being arranged in the horizontal direction.

10. The method of claim 1 , wherein each of the plurality of S/D local interconnects is positioned at two sides of a respective gate electrode of the plurality of gate electrodes.

Assignees

• Tokyo Electron Ltd

Inventors

• Liebmann Lars
• Smith Jeffrey
• Devilliers Anton J
• Tapily Kandabara

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D89/10

  Integrated device layouts · CPC title