3D semiconductor devices and methods of fabricating same

Patent metadata

Field	Value
Publication number	US-9355913-B2
Application number	US-201314047578-A
Country	US
Kind code	B2
Filing date	Oct 7, 2013
Priority date	Nov 17, 2010
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a plurality of vertical channels on a substrate; and
forming a gate stack having a stair-stepped structure on the substrate, the gate stack including vertically spaced apart conductive layers constituting gates, respectively, insulating layers each interposed between respective ones of the conductive layers, and an electrical conductor integral with first and second ones of the gates at lateral sides of the first and second gates so as to electrically connect the first and second gates,
wherein the vertical channels extend vertically through the gate stack;
the first and second gates are uppermost ones of the gates or lowermost ones of the,
the insulating layers include a first insulating layer interposed between the first and second gates and having a lateral surface, and a second insulating layer disposed on the second gate and having a lateral surface vertically aligned with the lateral surface of the first insulating layer,
the forming of the electrical conductor comprises forming electrically conductive material along the lateral surface of the first insulating layer,
whereby a multi-layered structure constituted by the first and second gates and the electrical conductor is formed.

2. The method of claim 1 , wherein the forming of the gate stack comprises:
forming a mold stack of a plurality of sacrificial layers spaced apart from one another on the substrate;
patterning the mold stack; and
replacing the sacrificial layers with conductive layers to form the gates.

3. The method of claim 2 , wherein the patterning of the mold stack comprises etching the sacrificial layers using sequentially decreasing or increasing masks so as to repeatedly and sequentially form steps in the stack of sacrificial layers.

4. The method of claim 3 , wherein the patterning of the mold stack comprises simultaneously patterning a first one of the sacrificial layers and a second one of the sacrificial layers disposed adjacent to and under the first sacrificial layer to thereby form first and second sacrificial layer patterns; and
the forming of the electrical conductor comprises forming a connection layer pattern making contact with lateral end surfaces of the first and second sacrificial layer patterns, and
replacing the connection layer pattern with electrically conductive material,
whereby the multi-layered structure is a one-piece structure constituted by the first and second gates and the electrical conductor.

5. The method of claim 4 , wherein the forming of the connection layer pattern comprises:
forming a connection layer on the mold stack from a material having at least one of a same composition and a same etch selectivity as the sacrificial layers; and
anisotropically etching the connection layer to form the connection layer pattern on the lateral end surfaces of the first and second sacrificial layer patterns.

6. The method of claim 4 , wherein the thickness of at least one of the first and second sacrificial layers is different from the thickness of each of the other sacrificial layers.

7. The method of claim 1 , wherein the forming of the gate stack comprises:
forming a stack of vertically spaced apart conductive layers on the substrate; and
forming the stair-stepped structure by patterning the stack of conductive layers, and thereby forming the gates.

8. The method of claim 7 , wherein the patterning of the stack of conductive layers comprises sequentially etching the conductive layers using sequentially decreasing or increasing masks so as to repeatedly and sequentially form steps in the stack of conductive layers.

9. The method of claim 7 , wherein the patterning of the stack of conductive layers comprises patterning a first one of the conductive layers and a second one of the conductive layers disposed adjacent to and under the first conductive layer to thereby form patterned first and second conductive layers constituting the first and second gates, respectively; and
the forming of the electrical conductor comprises forming a conductive spacer integrally with lateral surfaces of the patterned first and second conductive layers.

10. The method of claim 9 , wherein the forming of the conductive spacer comprises:
forming a conductive spacer layer on the mold stack using a material having a same composition as that of the conductive layers; and
anisotropically etching the conductive spacer layer to form the conductive spacer on the lateral surfaces of the patterned first and second conductive layers.

11. The method of claim 9 , wherein the thickness of each of the first and second conductive layers is different from the thickness of each of the other conductive layers.

12. The method of claim 4 , wherein the first and second sacrificial layer patterns are replaced with respective ones of the conductive layers at the same time the connection layer pattern is replaced with the electrically conductive material.

13. The method of claim 1 , wherein the forming of the electrical conductor comprises forming the electrically conductive material in contact with the lateral surface of the first insulating layer.

14. A method of fabricating a semiconductor device, the method comprising:
forming a plurality of vertical channels on a substrate; and
forming a gate stack having a stair-stepped structure on the substrate, the gate stack including a plurality of vertically spaced apart layers constituting gates, respectively, and an electrical conductor integral with first and second ones of the gates,
wherein the vertical channels extend vertically through the gate stack;
the first and second gates are uppermost ones of the gates or lowermost ones of the gates;
the forming of the gate stack comprises:
forming a mold stack of a plurality of sacrificial layers spaced apart from one another on the substrate,
patterning the mold stack by etching the sacrificial layers using sequentially decreasing or increasing masks so as to repeatedly and sequentially form steps in the stack of sacrificial layers, and the patterning of the mold stack includes simultaneously patterning a first one of the sacrificial layers and a second one of the sacrificial layers disposed adjacent to and under the first sacrificial layer to thereby form first and second sacrificial layer patterns, and
replacing the sacrificial layers with electrically conductive layers to form the gates; and
the forming of the electrical conductor comprises:
forming a connection layer pattern making contact with lateral end surfaces of the first and second sacrificial layer patterns, and
replacing the connection layer pattern with electrically conductive material,
whereby the multi-layered structure is a one-piece structure constituted by the first and second gates and the electrical conductor.

15. The method of claim 14 , wherein the forming of the connection layer pattern comprises:
forming a connection layer on the mold stack from a material having at least one of a same composition and a same etch selectivity as the sacrificial layers, and
anisotropically etching the connection layer to form the connection layer pattern on the lateral end surfaces of the first and second sacrificial layer patterns.

16. The method of claim 14 , wherein the thickness of at least one of the first and second sacrificial layers is different from the thickness of each of the other sacrificial layers.

17. The method of claim 14 , wherein the first and second sacrificial layer patterns are replaced with respective ones of t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sang-Yong
• Park Jintaek
• Kim Hansoo
• Chung Juhyuck
• Cho Wonseok

Classifications

• H10D30/693 Primary

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title

• H01L27/11582

  Electricity · mapped topic