Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors

Patent metadata

Field	Value
Publication number	US-9543318-B1
Application number	US-201514832579-A
Country	US
Kind code	B1
Filing date	Aug 21, 2015
Priority date	Aug 21, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

An alternating stack of insulator layers and spacer material layers is formed over a substrate. Stepped surfaces are formed in a contact region in which contact via structures are to be subsequently formed. An epitaxial semiconductor pedestal can be formed by a single epitaxial deposition process that is performed after formation of the stepped surfaces and prior to formation of memory openings, or a combination of a first epitaxial deposition process performed prior to formation of memory openings and a second epitaxial deposition process performed after formation of the memory openings. The epitaxial semiconductor pedestal can have a top surface that is located above a topmost surface of the alternating stack. The spacer material layers are formed as, or can be replaced with, electrically conductive layers. Backside contact via structures can be subsequently formed.

First claim

What is claimed is:

1. A method of fabricating a memory device, comprising:
forming an alternating stack of insulator layers and spacer material layers over a single crystalline semiconductor surface of a substrate;
forming stepped surfaces by patterning the alternating stack, wherein the single crystalline semiconductor surface is exposed in a region from which all layers of the alternating stack are removed;
after forming the stepped surfaces, forming an epitaxial semiconductor pedestal and a dielectric material portion over a semiconductor surface of the semiconductor substrate and over the stepped surfaces, respectively, wherein the epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor surface of the substrate;
forming an array of memory stack structures through a remaining portion of the alternating stack;
forming at least one semiconductor device on the epitaxial semiconductor pedestal;
forming a planarization stopping layer over the alternating stack;
patterning the planarization stopping layer prior to forming the stepped surfaces;
depositing a dielectric material over the patterned planarization stopping layer, the stepped surfaces and the epitaxial semiconductor pedestal; and
planarizing the dielectric material using the epitaxial semiconductor pedestal and the planarization stopping layer a stopping structures to form the dielectric material portion,
wherein the epitaxial semiconductor pedestal is formed by a selective epitaxy process prior to formation of the dielectric material portion.

2. The method of claim 1 , wherein:
forming at least one semiconductor device on the epitaxial semiconductor pedestal comprises forming at least one transistor of a driver circuit of the memory device on the epitaxial semiconductor pedestal; and
the epitaxial semiconductor pedestal has substantially vertical sidewalls.

3. The method of claim 2 , wherein the epitaxial semiconductor pedestal sidewalls lack stepped structures.

4. The method of claim 1 , wherein each of the memory stack structures comprises:
a memory film including tunneling dielectric, at least one charge storage region and a blocking dielectric; and
a vertical semiconductor channel contacting an inner surface of the memory film and overlying the single crystalline semiconductor surface of the substrate.

5. The method of claim 1 , wherein:
the spacer material layers are provided as, or are replaced with, electrically conductive layers; and
the method further comprises forming contact via structures through the dielectric material portion to a respective electrically conductive layer.

6. A method of fabricating a memory device, comprising:
forming an alternating stack of insulator layers and spacer material layers over a single crystalline semiconductor surface of a substrate;
forming stepped surfaces by patterning the alternating stack, wherein the single crystalline semiconductor surface is exposed in a region from which all layers of the alternating stack are removed;
after forming the stepped surfaces, forming an epitaxial semiconductor pedestal and a dielectric material portion over a semiconductor surface of the semiconductor substrate and over the stepped surfaces, respectively, wherein the epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor surface of the substrate;
forming an array of memory stack structures through a remaining portion of the alternating stack; and
forming at least one semiconductor device on the epitaxial semiconductor pedestal,
wherein the dielectric material portion is formed by deposition and patterning of a dielectric material prior to formation of the epitaxial semiconductor pedestal, and
wherein the epitaxial semiconductor pedestal is formed by:
performing a first epitaxial semiconductor deposition process that forms a lower epitaxial semiconductor pedestal portion; and
performing a second epitaxial semiconductor deposition process that forms an upper epitaxial semiconductor pedestal portions, wherein the lower and upper epitaxial semiconductor pedestal portions collectively constitute the epitaxial semiconductor pedestal.

7. The method of claim 6 , further comprising:
forming a plurality of memory openings through the remaining portion of the alternating stack after the first epitaxial semiconductor deposition process and prior to the second epitaxial semiconductor deposition process; and
forming an array of epitaxial channel portions in the plurality of memory openings during the second epitaxial semiconductor deposition process that forms the upper epitaxial semiconductor pedestal portions.

8. The method of claim 7 , wherein forming the array of memory stack structures comprises forming the array of memory stack structures in the respective memory openings on the an array of epitaxial channel portions.

9. A method of fabricating a memory device, comprising:
forming an alternating stack of insulator layers and spacer material layers over a single crystalline semiconductor surface of a substrate;
forming a planarization stopping layer over the alternating stack;
forming stepped surfaces by patterning the alternating stack, wherein the single crystalline semiconductor surface is exposed in a region from which all layers of the alternating stack are removed;
after forming the stepped surfaces, forming an epitaxial semiconductor pedestal and a dielectric material portion over a semiconductor surface of the semiconductor substrate and over the stepped surfaces, respectively, wherein the epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor surface of the substrate;
planarizing a topmost surface of the epitaxial semiconductor pedestal employing the planarization stopping layer as a stopping layer;
forming an array of memory stack structures through a remaining portion of the alternating stack; and
forming at least one semiconductor device on the epitaxial semiconductor pedestal.

10. A method of fabricating a memory device, comprising:
forming an alternating stack of insulator layers and spacer material layers over a single crystalline semiconductor surface of a substrate;
forming steeped surfaces by patterning the alternating stack, wherein the single crystalline semiconductor surface is exposed in a region from which all layers of the alternating stack are removed;
after forming the stepped surfaces, forming an epitaxial semiconductor pedestal and a dielectric material portion over a semiconductor surface of the semiconductor substrate and over the stepped surfaces, respectively, wherein the epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor surface of the substrate;
forming an array of memory stack structures through a remaining portion of the alternating stack; and
forming at least one semiconductor device on the epitaxial semiconductor pedestal;
forming a plurality of dummy openings through the stepped surfaces;
forming a plurality of dummy memory stack structures in the plurality of dummy openings at the same time as forming the array of memory stack structures; and
forming a plurality of bit lines in electrical contact with the array of memory stack structures, such that the plurality of dummy memory stack structures are not in electrical contact with the plurality of bit lines,
wherein each of the memory stack structures comprises:
a memory film including tunneling dielectric, at least one charge storage region and a blocking dielectric; and
a vertical semiconductor channel contacting an inner surface of the memory film and overlying the single crystalline semiconductor surfa

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Lu Zhenyu
• Mao Daxin
• Miyata Koji
• Ariyoshi Junichi
• Alsmeier Johann
• Matamis George
• Shi Wenguang
• Xu Jiyin
• Hu Xiaolong

Classifications

• H01L29/7926

  Electricity · mapped topic

• H01L21/28282

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L29/66833

  Electricity · mapped topic

• H01L29/4234

  Electricity · mapped topic