Semiconductor devices and methods of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9419003-B1
Application number	US-201514713948-A
Country	US
Kind code	B1
Filing date	May 15, 2015
Priority date	May 15, 2015
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

An SRAM cell includes a first vertical pull-up transistor stacked atop a first vertical pull-down transistor, and a second vertical pull-up transistor stacked atop a second vertical pull-down transistor. The gates of the first vertical pull-up transistor and the first vertical pull-down transistor are coupled by a first via, while the gates of the second vertical pull-up transistor and the second vertical pull-down transistor are coupled by a second via. Gates of the first vertical pull-up transistor and a first vertical pass-gate transistor are coupled by a first conductive trace, while gates of the second vertical pull-up transistor and a second vertical pass-gate transistor are coupled by a second conductive trace. The gate of the first vertical pull-up transistor is coupled to the second conductive trace by a third via, while the gate of the second vertical pull-up transistor is coupled to the first conductive trace by a fourth via.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first pull-down transistor comprising a first vertical source, a first vertical channel above the first vertical source, a first vertical drain above the first vertical channel, and a first gate electrode around the first vertical channel;
a first pull-up transistor comprising a second vertical drain above the first vertical drain, a second vertical channel above the second vertical drain, a second vertical source above the second vertical channel, and a second gate electrode around the second vertical channel;
a first via coupling the first gate electrode and the second gate electrode;
a first conductive trace having a first portion between the first vertical drain and the second vertical drain;
a first pass-gate transistor comprising a third vertical source, a third vertical channel above the third vertical source, a third vertical drain above the third vertical channel, and a third gate electrode around the third vertical channel, the first conductive trace having a second portion over the third vertical drain;
a second pull-down transistor comprising a fourth vertical source, a fourth vertical channel above the fourth vertical source, a fourth vertical drain above the fourth vertical channel, and a fourth gate electrode around the fourth vertical channel;
a second pull-up transistor comprising a fifth vertical drain above the fourth vertical drain, a fifth vertical channel above the fifth vertical drain, a fifth vertical source above the fifth vertical channel, and a fifth gate electrode around the fifth vertical channel, the fifth gate electrode having a distal portion extending over the second portion of the first conductive trace;
a second via coupling the fourth gate electrode and the fifth gate electrode;
a second conductive trace having a first portion between the fourth vertical drain and the fifth vertical drain;
a second pass-gate transistor comprising a sixth vertical source, a sixth vertical channel above the sixth vertical source, a sixth vertical drain above the sixth vertical channel, and a sixth gate electrode around the sixth vertical channel, the second conductive trace having a second portion over the sixth vertical drain, the second gate electrode having a distal portion extending over the second portion of the second conductive trace;
a third via coupling the distal portion of the second gate electrode and the second portion of the second conductive trace; and
a fourth via coupling the distal portion of the fifth gate electrode and the second portion of the first conductive trace.

2. The semiconductor device of claim 1 , wherein the first pass-gate transistor is laterally separated from the first pull-down transistor along a first direction by a first distance, wherein the second pass-gate transistor is laterally separated from the first pull-down transistor along a second direction substantially perpendicular to the first direction by substantially the first distance, and wherein second pull-down transistor is laterally separated from the first pass-gate transistor along the second direction by substantially the first distance.

3. The semiconductor device of claim 2 , wherein the first distance is a minimum printable pitch of the semiconductor device.

4. The semiconductor device of claim 1 , wherein at least one of the first pull-up transistor or the second pull-up transistor comprises a vertical junctionless transistor.

5. The semiconductor device of claim 4 , wherein the vertical junctionless transistor comprises a polycrystalline semiconductor material.

6. The semiconductor device of claim 1 , wherein at least one of the first conductive trace or the second conductive trace comprises a silicide.

7. The semiconductor device of claim 1 , wherein the second vertical drain is aligned with the first vertical drain, and wherein the fifth vertical drain is aligned with the fourth vertical drain.

8. The semiconductor device of claim 1 , further comprising a word line coupled to the third gate electrode and the sixth gate electrode.

9. The semiconductor device of claim 1 , further comprising:
a first n-well, the first vertical source extending from the first n-well;
a second n-well laterally separated from the first n-well by a first distance, the third vertical source extending from the second n-well;
a third n-well laterally separated from the second n-well by the first distance, the fourth vertical source extending from the third n-well; and
a fourth n-well laterally separated from the first n-well and the third n-well by the first distance, the sixth vertical source extending from the fourth n-well.

10. The semiconductor device of claim 9 , further comprising:
a first power via coupled to the first n-well; and
a second power via coupled to the third n-well, wherein the first power via and the second power via are coupled to a power rail.

11. A semiconductor device, comprising:
a first vertical pull-down transistor in a first active level of the semiconductor device, the first vertical pull-down transistor comprising a first gate electrode extending laterally in the first active level;
a first vertical pull-up transistor stacked over the first vertical pull-down transistor, the first vertical pull-up transistor in a second active level of the semiconductor device and having a second gate electrode extending laterally in the second active level;
a first via coupling the first gate electrode in the first active level and the second gate electrode in the second active level;
a first conductive trace disposed between the first vertical pull-down transistor and the first vertical pull-up transistor, the first conductive trace coupling drain regions of the first vertical pull-down transistor and the first vertical pull-up transistor to each other;
a second vertical pull-down transistor in the first active level of the semiconductor device, the second vertical pull-down transistor comprising a third gate electrode extending laterally in the first active level;
a second vertical pull-up transistor stacked over the second vertical pull-down transistor, the second vertical pull-up transistor in the second active level of the semiconductor device and having a fourth gate electrode extending laterally in the second active;
a second via coupling the third gate electrode in the first active level and the fourth gate electrode in the second active level;
a second conductive trace disposed between the second vertical pull-down transistor and the second vertical pull-up transistor, the second conductive trace coupling drain regions of the second vertical pull-down transistor and the second vertical pull-up transistor to each other;
a first vertical pass-gate transistor in the first active level of the semiconductor device, wherein a portion of the first conductive trace extends over and contacts a drain region of the first vertical pass-gate transistor;
a second vertical pass-gate transistor in the first active level of the semiconductor device, wherein a portion of the second conductive trace extends over and contacts a drain region of the second vertical pass-gate transistor;
a third via interconnecting the portion of the second conductive trace contacting the drain region of the second vertical pass-gate transistor and a portion of the second gate electrode extending over the second vertical pass-gate transistor; and
a fourth via interconnecting the portion of the first conductive trace contacting the drain region of the first vertical pass-gate transistor and a portion of the fourth gate electrode extending over the first vertical pass-gate transistor.

12. The semiconductor devi

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Colinge Jean-Pierre
• Diaz Carlos H
• Guo Ta-Pen

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D84/0195

  the components including vertical IGFETs · CPC title