Three-dimensionally integrated circuit devices including oxidation suppression layers

Patent metadata

Field	Value
Publication number	US-9911745-B2
Application number	US-201715426081-A
Country	US
Kind code	B2
Filing date	Feb 7, 2017
Priority date	Oct 8, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.

First claim

What is claimed is:

1. A method of fabricating a three-dimensional semiconductor memory device, comprising:
providing a substrate including a cell array region and a peripheral circuit region;
forming a doped layer doped with an impurity on the substrate of the cell array region to terminate a surface of the doped layer with a species of the impurity;
forming a mold structure on the doped layer, the mold structure including a buffer insulating layer on the doped layer, and insulating layers and sacrificial layers alternately and vertically stacked on the buffer insulating layer; and
forming a plurality of vertical structures passing through the mold structure.

2. The method of claim 1 , wherein the impurity includes carbon C, nitrogen N, or fluorine F.

3. The method of claim 1 , wherein the doped layer is in contact with the buffer insulating layer.

4. The method of claim 1 , further comprising forming a peripheral logic structure on the peripheral circuit region of the substrate before forming the doped layer,
wherein forming the peripheral logic structure comprises:
forming peripheral logic circuits on the peripheral circuit region of the substrate;
forming a peripheral insulating layer covering the substrate provided with the peripheral logic circuits; and
patterning the peripheral insulating layer to form a peripheral insulating pattern exposing the cell array region of the substrate.

5. The method of claim 4 , wherein the doped layer is doped in situ during the forming the peripheral insulating pattern.

6. The method of claim 4 , wherein the doped layer is formed by implanting the impurity into the substrate of the cell array region.

7. The method of claim 1 , wherein forming the vertical structures comprises:
forming vertical holes passing through the mold structure and the doped layer to expose the substrate;
forming lower semiconductor patterns in lower regions of the vertical holes to connect to the substrate by performing a selective epitaxial growth (SEG) process; and
forming upper semiconductor patterns in upper regions of the vertical holes to connected to the lower semiconductor patterns.

8. The method of claim 1 , further comprising replacing the sacrificial layers with conductive layers after forming the vertical structures.

9. The method of claim 8 , wherein the replacing of the sacrificial layers with the conductive layers comprises:
forming a trench penetrating the mold structure to be spaced apart from the vertical structures;
removing the sacrificial layers exposed by the trench to form gate regions between the insulating layers; and
forming the conductive layers in the gate regions, respectively.

10. The method of claim 9 , further comprising forming a vertical gate insulating layer on a portion of a lower semiconductor pattern between the insulating layers vertically adjacent to each other before forming the conductive layers,
wherein the vertical gate insulating layer is a silicon oxide layer.

11. The method of claim 10 , wherein forming the vertical gate insulating layer comprises performing a thermal oxidation process after forming the gate regions.

12. The method of claim 10 , further comprising forming a blocking insulating layer conformally covering inner surfaces of the gate regions after forming the vertical gate insulating layer.

13. The method of claim 10 , wherein the substrate includes a connection region between the cell array region and the peripheral circuit region,
the mold structure and the doped layer extend from the cell array region to the connection region,
the mold structure on the connection region has a staircase structure, and
a thickness of the mold structure on the connection region decreases stepwise in a direction toward the peripheral circuit region.

14. The method of claim 13 , further comprising:
oxidizing the buffer insulating layer to form a horizontal gate insulating layer from the buffer insulating layer, wherein the horizontal gate insulating layer has substantially equal thickness in the cell array region and in the connection region after forming the vertical gate insulating layer.

15. The method of claim 13 , further comprising forming dummy vertical structures penetrating the mold structure in a connection region between the cell array region and the peripheral circuit region.

16. A method of fabricating a three-dimensional semiconductor memory device, comprising:
providing a substrate including a cell array region and a peripheral circuit region;
forming a doped impurity layer on the substrate in the cell array region;
forming a buffer insulating layer on the doped layer to have a first thickness;
forming a mold structure on the buffer insulating layer, the mold structure including insulating layers and sacrificial layers alternately and vertically stacked on the buffer insulating layer;
removing the sacrificial layers to expose the buffer insulating layer; and
forming a horizontal gate insulating layer from the buffer insulating layer, wherein the horizontal gate insulating layer has a second thickness that is greater than the first thickness.

17. The method of claim 16 wherein forming the doped impurity layer on the substrate in the cell array region comprises doping the substrate with carbon C, nitrogen N, or fluorine F.

18. A method of fabricating a three-dimensional semiconductor memory device, comprising:
providing a substrate including a cell array region and a peripheral circuit region;
forming an oxidation suppressing layer on the substrate of the cell array region;
forming a mold structure on the oxidation suppressing layer, the mold structure including a buffer insulating layer on the oxidation suppressing layer, and insulating layers and sacrificial layers alternately and vertically stacked on the buffer insulating layer; and
forming a plurality of vertical structures passing through the mold structure.

19. The method of claim 18 , wherein forming the oxidation suppressing layer comprises doping the substrate with impurities comprising carbon C, nitrogen N, or fluorine F.

20. The method of claim 18 , further comprising:
oxidizing the buffer insulating layer to form a horizontal gate insulating layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dong Sik
• Kim Youngwoo
• Shin Jinhyun
• Lee Jung Hoon

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10D64/01332

  Making the insulator · CPC title

• H01L27/1104

  Electricity · mapped topic

• H01L21/823462

  Electricity · mapped topic