Top-down self-alignment of vias in a semiconductor device for sub-22NM pitch metals
US-12564027-B2 · Feb 24, 2026 · US
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Devilliers Anton J patents
Devilliers Anton J is listed as an inventor on 259 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Devilliers Anton J |
| Total patents | 259 |
| First publication | Jan 15, 2015 |
| Latest publication | Feb 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Coaxial see-through inspection system
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Method for selective exposure of wafer to corrective irradiation at a per-die level
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Method for chuck compensation via wafer shape control
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Wet-dry bilayer resist
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Method to form narrow slot contacts
US-12488989-B2 · Dec 2, 2025 · US
In-situ lithography pattern enhancement with localized stress treatment tuning using heat zones
US-12455511-B2 · Oct 28, 2025 · US
Die shape control for die to wafer bond enhancement
US-2025259943-A1 · Aug 14, 2025 · US
Hybrid patterning-bonding semiconductor tool
US-12381093-B2 · Aug 5, 2025 · US
Method for selective exposure of wafer to corrective irradiation at a per-die level
US-2025244680-A1 · Jul 31, 2025 · US
Recent patents
Latest publications not already listed above.
Wafer shape control for W2W bonding
US-12374562-B2 · Jul 29, 2025 · US
Wet-dry bilayer resist dual tone exposure
US-12327726-B2 · Jun 10, 2025 · US
Backside deposition tuning of stress to control wafer bow in semiconductor processing
US-12276922-B2 · Apr 15, 2025 · US
Selective patterning with wet-dry bilayer resist
US-12249508-B2 · Mar 11, 2025 · US
Power delivery network for CFET with buried power rails
US-12040271-B2 · Jul 16, 2024 · US
Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks
US-12020990-B2 · Jun 25, 2024 · US
Precision multi-axis photolithography alignment correction using stressor film
US-12001147-B2 · Jun 4, 2024 · US
Method for tuning stress transitions of films on a substrate
US-11990334-B2 · May 21, 2024 · US
Method for producing overlay results with absolute reference for semiconductor manufacturing
US-11966171-B2 · Apr 23, 2024 · US
Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory
US-11901360-B2 · Feb 13, 2024 · US
System and Method for Liquid Dispense and Coverage Control
US-2024042472-A1 · Feb 8, 2024 · US
System and method for liquid dispense and coverage control
US-11883837-B2 · Jan 30, 2024 · US
Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking
US-11862497-B2 · Jan 2, 2024 · US
Method for pattern reduction using a staircase spacer
US-11854806-B2 · Dec 26, 2023 · US
Method of forming a narrow trench
US-11841617-B2 · Dec 12, 2023 · US
Multi-dimensional vertical switching connections for connecting circuit elements
US-11810854-B2 · Nov 7, 2023 · US
Top-down self-alignment of vias in a semiconductor device for sub-22nm pitch metals
US-2023352343-A1 · Nov 2, 2023 · US
Hybrid patterning-bonding semiconductor tool
US-2023326814-A1 · Oct 12, 2023 · US
Method for chuck compensation via wafer shape control
US-2023326738-A1 · Oct 12, 2023 · US
Wafer shape control for w2w bonding
US-2023326767-A1 · Oct 12, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Tokyo Electron Ltd | 242 |
| Micron Technology Inc | 18 |
| Jain Kaveri | 1 |
| Olson Adam L | 1 |
| Brown William R | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10P76/2041 | 74 |
| H10P76/4085 | 52 |
| H10D84/038 | 49 |
| H10W20/089 | 48 |
| H10P74/23 | 44 |