Silicide structures in transistors and methods of forming

US11855169B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11855169-B2
Application numberUS-202217826673-A
CountryUS
Kind codeB2
Filing dateMay 27, 2022
Priority dateMay 22, 2020
Publication dateDec 26, 2023
Grant dateDec 26, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

First claim

Opening claim text (preview).

What is claimed is: 1. A device comprising: a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide comprising: a conformal first portion extending into the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen, wherein the silicide comprises chlorine; and a source/drain contact electrically connected to the source/drain region through the silicide. 2. The device of claim 1 , wherein the metal is titanium, the conformal first portion comprises titanium silicon (TiSi), and the conformal second portion comprises titanium silicon nitrogen (TSN). 3. The device of claim 1 , wherein a thickness of the conformal first portion is in a range of 2 nm to 4 nm. 4. The device of claim 1 , wherein a thickness of the conformal second portion is in a range of 1 nm to 2 nm. 5. The device of claim 1 , wherein the source/drain contact comprises: a liner; and a metal over the liner. 6. The device of claim 1 , wherein the conformal first portion and the conformal second portion of the silicide each comprises chlorine. 7. The device of claim 6 , wherein the chlorine in the silicide is less than 0.5% atomic. 8. A device comprising: a gate stack over a channel region of a transistor; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the channel region; a silicide extending into the source/drain region, the silicide comprising: a titanium silicon portion, wherein a ratio of a minimum thickness of the titanium silicon portion to a maximum thickness of the titanium silicon portion is in a range of 3.5:1 to 5:1; and a titanium silicon nitride portion on the titanium silicon portion, wherein a ratio of a minimum thickness of the titanium silicon nitride portion to a maximum thickness of titanium silicon nitride portion is in a range of 1:1 to 1.5:1; and a source/drain contact electrically connected to the source/drain region to the silicide. 9. The device of claim 8 , wherein the titanium silicon nitride portion extends above and along sides of the titanium silicon portion. 10. The device of claim 8 , wherein the titanium silicon nitride portion extends along sidewalls of the gate spacer. 11. The device of claim 8 further comprising a first interlayer dielectric (ILD) around the gate stack, wherein the silicide extends along sidewalls of the first ILD. 12. The device of claim 11 further comprising a second ILD over the first ILD and the gate stack, wherein the silicide extends along sidewalls of the second ILD. 13. A device comprising: a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a contact etch stop layer over the source/drain region an interlayer dielectric (ILD) over the contact etch stop layer and around the source/drain region; a silicide over and extending into the source/drain region, the silicide comprising: a first portion extending into the source/drain region, the first portion comprising a metal and silicon, wherein the first portion extends along the contact etch stop layer; and a second portion over the first portion, the second portion further disposed on the sidewall of the gate spacer, the second portion comprising the metal, silicon, and nitrogen, wherein the second portion extends to a top surface of the ILD; and a source/drain contact electrically connected to the source/drain region through the silicide. 14. The device of claim 13 , wherein the metal is titanium. 15. The device of claim 13 , wherein a thickness of the first portion is in a range of 2 nm to 4 nm. 16. The device of claim 15 , wherein a thickness of the second portion is in a range of 1 nm to 2 nm. 17. The device of claim 13 further comprising a dielectric layer on the ILD, wherein the second portion extends to a top surface of the dielectric layer. 18. The device of claim 13 , wherein the second portion lines sidewalls of the source/drain contact. 19. The device of claim 18 , wherein the source/drain contact comprises: a barrier layer on the second portion of the silicide; and a fill metal on the barrier layer. 20. The device of claim 13 , wherein the silicide comprises chlorine.

Assignees

Inventors

Classifications

  • in openings in dielectrics · CPC title

  • by using plasmas or gaseous environments, e.g. by nitriding · CPC title

  • Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

  • using selective deposition · CPC title

  • using conductive layers comprising silicides · CPC title

Patent family

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Frequently asked questions

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What does patent US11855169B2 cover?
A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second p…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd, Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D64/0112. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 26 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).