Self-aligned scheme for semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-11830770-B2
Application number	US-202217749303-A
Country	US
Kind code	B2
Filing date	May 20, 2022
Priority date	Sep 26, 2019
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

First claim

What is claimed is:

1. A device comprising:
a first dielectric layer disposed on a substrate;
a first conductive component at least partially embedded in the first dielectric layer;
a second dielectric layer disposed on the first dielectric layer, wherein at least a portion of a top surface of the first conductive component is recessed relative to respective top surfaces of the first and second dielectric layers;
a capping layer disposed directly on the top surface of the first conductive component such that the capping layer physically contacts the top surface of the first conductive component;
an etch stop layer disposed directly on the second dielectric layer and the capping layer such that the etch stop layer physically contacts the second dielectric layer and the capping layer; and
a second conductive component disposed directly on the first conductive component, wherein the second conductive component physically contacts the first conductive component, the second dielectric layer, the etch stop layer and the capping layer.

2. The device of claim 1 , wherein the first conductive component includes a first metal line and the second conductive component includes a via and a second metal line.

3. The device of claim 1 , wherein the second dielectric layer includes a material selected from the group consisting of silicon carbide (SiC), silicon dioxide (SiO 2 ), silicon oxy-carbide (SiOC), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxy-nitride (SiON), silicon oxy-carbonitride (SiOCN).

4. The device of claim 1 , wherein the second dielectric layer is thicker than the capping layer.

5. The device of claim 1 , wherein the first conductive component includes a barrier layer and a conductive fill material, and
wherein the conductive fill material has a top surface that is recessed relative to a top surface of the barrier layer.

6. The device of claim 5 , wherein the top surface of the barrier layer and the top surface of the first dielectric layer are positioned at the same height above the substrate.

7. The device of claim 1 , wherein the second conductive component includes a barrier layer and conductive material, and
wherein the barrier layer physically contacts the first conductive component, the second dielectric layer, the etch stop layer and the capping layer.

8. The device of claim 1 , wherein the etch stop layer includes:
a first etch stop layer physically contacting the second dielectric layer, the capping layer and the second conductive component, and
a second etch stop layer physically contacting the first etch stop layer and the second conductive component.

9. A device comprising:
an first dielectric layer disposed on a substrate;
a first conductive feature disposed in the first dielectric layer, wherein a top surface of the first conductive feature is recessed relative to the top surface of the first dielectric layer;
a first barrier layer disposed in the first dielectric layer between the first conductive feature and the first dielectric layer, the first barrier layer having a sidewall surface interfacing with the first conductive feature;
a capping layer disposed directly on the top surface of the first conductive feature and interfacing with the sidewall surface of the first barrier layer;
a second dielectric layer disposed directly on the top surface of the first dielectric layer; and
an etch stop layer extending form over the second dielectric to the capping layer, wherein the etch stop layer interfaces with the sidewall surface of the first barrier layer.

10. The device of claim 9 , further comprising:
a third dielectric layer disposed on the second dielectric layer,
a second conductive feature extending through the third and second dielectric layers; and
a second barrier layer extending along the second conductive feature to the capping layer.

11. The device of claim 10 , wherein a portion of the second conductive feature and a portion of the second barrier layer are disposed directly over the second dielectric layer.

12. The device of claim 9 , wherein the etch stop layer includes more than one layer, and wherein at least one layer of the etch stop layer interfaces with the sidewall surface of the first barrier layer.

13. The device of claim 9 , wherein the second dielectric layer includes a first portion and a second portion that is spaced apart from the first portion,
wherein the first portion of the second dielectric layer has a first sidewall and the second portion of the second dielectric layer has a second sidewall that faces the first sidewall, and
wherein the etch stop layer interfaces with the first sidewall of the first portion of the second dielectric layer and the second barrier layer interfaces with the second sidewall of the second portion of the second dielectric layer.

14. The device of claim 9 , wherein a top surface of the first conductive feature is recessed relative to a top surface of the first barrier layer.

15. The device of claim 14 , wherein the etch stop layer interfaces with the top surface of the first barrier layer.

16. A method comprising:
forming a first conductive component in a first dielectric layer;
forming a capping layer directly on the first conductive component;
forming a blocking layer directly on the capping layer;
forming a second dielectric layer directly on the first dielectric layer;
after forming the second dielectric layer, removing at least a portion of the blocking layer to expose the capping layer; and
forming a second conductive component directly on the capping layer.

17. The method of claim 16 , wherein the forming of the second dielectric layer directly on the first dielectric layer occurs after the forming of the blocking layer directly on the capping layer.

18. The method of claim 16 , wherein the forming of the first conductive component in the first dielectric layer includes:
forming a first trench in the first dielectric layer;
forming a first barrier layer in the first trench; and
forming a first conductive material on the first barrier within the first trench, and
wherein the forming of the second conductive component directly on the capping layer includes:
forming a third dielectric layer over the second dielectric layer;
forming a second trench in the third dielectric layer;
forming a second barrier layer in the second trench; and
forming a second conductive material on the second barrier within the second trench.

19. The method of claim 16 , further comprising:
forming an etch stop layer directly on the exposed capping layer after the removing of at least the portion of the blocking layer to expose the capping layer, and
removing a portion of the etch stop layer to expose the capping layer prior to forming the second conductive component directly on the capping layer.

20. The method of claim 16 , wherein the forming of the blocking layer directly on the capping layer includes forming a self-assembling monolayer material directly on the capping layer, and
wherein the removing of at least the portion of the blocking layer to expose the capping layer includes performing a gas based treatment process to remove at least the portion of the blocking layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsueh Hsiu-Wen
• Wu cai-ling
• Tseng Ya-Ching
• Chen Chii-Ping
• Yang Neng-Jye

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title