Memory interface with configurable high-speed serial data lanes for high bandwidth memory

Patent metadata

Field	Value
Publication number	US-11810640-B2
Application number	US-202217666255-A
Country	US
Kind code	B2
Filing date	Feb 7, 2022
Priority date	Feb 10, 2021
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

A memory module including a memory array of storage transistors and a control circuit where the control circuit includes a memory interface for providing high bandwidth access to the memory array on serial data lanes. In some embodiments, the control circuit of a memory module includes multiple transceivers for connecting to serial data lanes. In one embodiment, the memory interface of a memory module configures some transceivers for host connection or for upstream connection to an upstream memory module and configures other transceivers for downstream connection to a downstream memory module. In other embodiments, a multi-module memory device is formed using multiple memory modules connected in a cascade configuration or in a star configuration to provide high bandwidth memory access to all memory locations of the multiple memory modules using the given number of serial data lanes of the host connection.

First claim

The invention claimed is:

1. A memory module, comprising:
a memory array of storage transistors; and
a control circuit for accessing and operating the memory array, the control circuit comprising a memory interface circuit, the memory interface circuit comprising a plurality of transceivers, each transceiver to be connected to a respective serial data lane, the memory interface circuit configuring a first subset of the transceivers for upstream connections for connecting through one or more serial data lanes to a host processor or connecting to transceivers of an upstream memory module and a second subset of the transceivers for downstream connections for connecting through one or more serial data lanes to transceivers of a downstream memory module,
wherein the control circuit receives a data packet from the host processor or the upstream memory module and inspects the memory address associated with the data packet, and in response to the control circuit determining the memory address of the data packet as not belonging to an address space associated with the memory array, the control circuit transmits the data packet onto one or more transceivers of the second subset to the downstream memory module.

2. The memory module of claim 1 , wherein the first subset of the transceivers of the control circuit connects to a host processor and the second subset of the transceivers of the control circuit connects to the transceivers of a first downstream memory module.

3. A memory module, comprising:
a memory array of storage transistors; and
a control circuit for accessing and operating the memory array, the control circuit comprising a memory interface circuit, the memory interface circuit comprising a plurality of transceivers, each transceiver to be connected to a respective serial data lane, the memory interface circuit configuring a first subset of the transceivers for upstream connections for connecting through one or more serial data lanes to a host processor or connecting to transceivers of an upstream memory module and a second subset of the transceivers for downstream connections for connecting through one or more serial data lanes to transceivers of a downstream memory module,
wherein the control circuit receives data packets from the host processor or the upstream memory module and transmits the data packets onto the one or more transceivers of the second subset to the downstream memory module, the control circuit of the memory module and the control circuit of the downstream memory module each inspect the memory addresses associated with the data packets, and in response to the respective control circuit determining the memory address of a given data packet as not belonging to an address space associated with the respective memory array, the respective control circuit ignores the data packet.

4. The memory module of claim 2 , wherein the control circuit receives a data packet from the first downstream memory module and transmits the data packet onto one or more transceivers of the first subset to the host processor.

5. The memory module of claim 4 , wherein the control circuit modifies the memory address of the data packet received from the first downstream memory module before transmitting the data packet to the host processor.

6. The memory module of claim 2 , wherein the control circuit receives a data packet from the host processor and inspects the memory address associated with the data packet, and in response to the control circuit determining the memory address of the data packet as belonging to an address space associated with the memory array, the control circuit processes the data packet and operates the memory array in response to the data packet.

7. The memory module of claim 2 , wherein the memory interface circuit configures the first subset of transceivers by negotiating with the host processor and configures the second subset of transceivers by negotiating with the first downstream memory module upon powering up of the memory module.

8. The memory module of claim 2 , wherein the memory interface circuit queries the first downstream memory module for parameters associated with the first downstream memory module and determines a configuration of the memory module relative to the first downstream memory module in response to the queries.

9. The memory module of claim 2 , wherein the control circuit of the memory module processes data packets having memory addresses belonging to an address space associated with its memory array and containing frequently accessed data and; and the control circuit of the first downstream memory module processes data packets having memory addresses belonging to an address space associated with its memory array and containing infrequently accessed data.

10. The memory module of claim 1 , wherein the first subset of the transceivers of the control circuit connects to the transceivers of a first upstream memory module and the second subset of the transceivers of the control circuit connects to the transceivers of a second downstream memory module.

11. The memory module of claim 10 , wherein the control circuit receives a data packet from the second downstream memory module and transmits the data packet onto one or more transceivers of the first subset to the first upstream memory module.

12. The memory module of claim 11 , wherein the control circuit modifies the memory address of the data packet received from the second downstream memory module before transmitting the data packet to the first upstream memory module.

13. The memory module of claim 10 , wherein the control circuit receives a data packet from the first upstream memory module and inspects the memory address associated with the data packet, and in response to the control circuit determining the memory address of the data packet as belonging to an address space associated with the memory array, the control circuit processes the data packet and operates the memory array in response to the data packet.

14. The memory module of claim 10 , wherein the memory interface circuit queries the second downstream memory module for parameters associated with the second downstream memory module and determines a configuration of the memory module relative to the second downstream memory module in response to the queries.

15. The memory module of claim 1 , wherein each transceiver of the memory interface circuit comprises:
a transmitter for transmitting data packets onto a respective serial data lane, the transmitter including a serializer to receive parallel data and to generate serial data for transmission onto the serial data lane; and
a receiver for receiving data packets from the serial data lane, the receiver including a deserializer to receive serial data from the serial data lane and to generate parallel data.

16. The memory module of claim 15 , each serial data lane comprises signaling wires in the transmitting direction and the receiving direction.

17. The memory module of claim 1 , wherein the first subset of transceivers has the same number of transceivers as the second subset of transceivers.

18. The memory module of claim 1 , wherein the memory interface circuit further configures a third subset of transceivers for connecting to transceivers of a third downstream memory module through one or more serial data lanes.

19. The memory module of claim 18 , wherein the first subset, the second subset and the third subset of transceivers have the same number of transceivers.

20. The memory module of claim 1 , wherein the memory arra

Assignees

• Sunrise Memory Corp

Inventors

• Gans Dean
• Ziv Aran

Classifications

• G11C7/1063 Primary

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1015

  Read-write modes for single port memories, i.e. having either a random port or a serial port · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title