Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays

Patent metadata

Field	Value
Publication number	US-10121553-B2
Application number	US-201615248420-A
Country	US
Kind code	B2
Filing date	Aug 26, 2016
Priority date	Sep 30, 2015
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

First claim

I claim:

1. A memory structure, comprising:
a semiconductor substrate having a substantially planar surface, wherein the semiconductor substrate has circuitry formed therein;
a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance along a first direction, wherein each stack of active strips comprises two or more active strips provided one on top of another on two or more isolated planes and being substantially aligned lengthwise with each other along a second direction substantially parallel to the planar surface, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between a second semiconductor layer and a third semiconductor layer each of a second conductivity type, the first, second and third semiconductor layers each comprise polysilicon or silicon germanium;
a charge-trapping material; and
a plurality of conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being within a group of the conductors that are provided between the first stack of active strips and the second stack of active strips and separated from each stack of active strips by the charge-trapping material, thereby forming in each active strip at least one NOR string, each NOR string including a plurality of thin film transistors, including two or more thin-film transistors, that are formed out of the first, the second and the third semiconductor layers of the active strip and their adjacent charge-trapping material and the conductors within the group, wherein (a) the first, second and third semiconductor layers in each active strip provide, respectively, channel, source and drain regions of the thin-film transistors, (b) the thin-film transistors of each active strip sharing source and drain regions in common, and (c) one of the shared source and shared drain regions is electrically isolated relative to the circuitry, except when one or more of a selected group of thin-film transistors formed in the active strip are rendered conducting to charge a parasitic or intrinsic capacitor of the electrically isolated shared region by a current through the other shared region to a predetermined voltage.

2. The memory structure of claim 1 , wherein the predetermined voltage is a voltage related to one of: program, program-inhibit, reading and erasing data operations of the thin-film transistors.

3. The memory structure of claim 2 , wherein the second semiconductor layer serves as a shared virtual voltage source and the third semiconductor layer serves as a common bit line for the thin-film storage transistors in each NOR string.

4. The memory structure of claim 1 , further comprising a second plurality of conductors formed along the first direction, the second plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors that serve as gate electrodes of the thin-film transistors.

5. The memory structure of claim 4 , wherein the second plurality of conductors are formed between the planar surface and the active strips, the memory structure further comprising a third plurality of conductors formed above the active strips along the first direction, the third plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors that serve as gate electrodes of the thin-film transistors.

6. The memory structure of claim 5 , wherein the selected ones of the first plurality of conductors that are connected to the second plurality of conductors and the selected ones of the first plurality of conductors that are connected to the third plurality of conductors are provided on opposite sides of an active strip.

7. The memory structure of claim 5 , wherein each thin-film storage transistor is associated with a numeric address, wherein the thin-film transistors associated with even addresses are connected to the second plurality of conductors and wherein the thin-film transistors associated with odd addresses are connected to the third plurality of conductors.

8. The memory structure of claim 1 , wherein each active strip further comprises at least one metallic layer that is in electrical contact with, and in substantial alignment lengthwise with, one or both of the second semiconductor layer and the third semiconductor layer.

9. The memory structure of claim 1 wherein each thin-film storage transistor has a native enhancement mode threshold voltage, for each conductor.

10. The memory structure of claim 9 wherein, during a read or program operation, only the conductor associated with an addressed thin-film storage transistor of a NOR string is raised for a period of time to the predetermined voltage required for the read or program operation, while conductors associated with all other thin-film storage transistors of the NOR string held at a voltage below a threshold voltage of an erased thin-film storage transistor.

11. The memory structure of claim 10 , wherein active strips on one or more planes other than on a plane associated with the addressed thin-film storage transistor have their second or third semiconductor layer pre-charged to an inhibit voltage.

12. The memory structure of claim 11 , wherein thin-film storage transistors associated with active strips on more than one plane have their respective source regions pre-charged to predetermined voltages and are then programmed in a single concurrent programming operation.

13. The memory structure of claim 12 wherein, during the concurrent programming operation, the second or third semiconductor layer of each active strip in each plane is pre-charged to the predetermined voltage, which is associated with a program or program-inhibit operation, programming voltage pulses are then applied to one or more addressed conductors, and wherein the concurrent programming operation is terminated after all thin-film storage transistors associated with the addressed conductors are read-verified to have reached their respective intended programmed states.

14. The memory structure of claim 12 wherein the second or third semiconductor layer of each active strip in one or more planes is concurrently pre-charged to the predetermined voltage, which is associated with a read operation, prior to carrying out one or more read operations of addressed thin-film storage transistors in one or more of the planes while the second or third semiconductor layer holds substantially the predetermined voltage by virtue of capacitance along its associated active strip.

15. The memory structure of claim 14 , wherein the predetermined voltages of active strips on one or more planes serve as virtual ground voltage sources that are electrically isolated from each other, thereby substantially avoiding ground bounce or current spikes when a multiplicity of the addressed thin-film storage transistors are concurrently read.

16. The memory structure of claim 1 , wherein data stored in one or more of the thin-film storage transistors have a data retention time shorter than a year and a program/erase cycle endurance greater than 10,000 program/erase cycles.

17. The memory structure of claim 1 , wherein data stored in one or more of the thin-film storage transistors represents a continuum of stored states in an analog memory.

18. The memory structure of claim 1 , wherein the electric

Assignees

• Harari Eli
• Sunrise Memory Corp

Inventors

• Harari Eli

Classifications

• G11C16/0416

  comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM · CPC title

• G11C16/3431 Primary

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

• G11C11/5635

  Erasing circuits · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title