3DIC based system with memory cells and transistors

Patent metadata

Field	Value
Publication number	US-9799761-B2
Application number	US-201615351389-A
Country	US
Kind code	B2
Filing date	Nov 14, 2016
Priority date	Mar 11, 2013
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A 3D IC based system, the system including: a first layer including first memory cells including first transistors, where the first transistors include first transistor channels; a second layer overlying the first layer, the second layer including second memory cells including second transistors, where the second transistors include second transistor channels, where the second layer includes vertically oriented doped regions, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the first transistor channels and at least one of the second transistor channels are directly coupled to at least one of the vertically oriented doped region.

First claim

What is claimed is:

1. A 3D IC based system, the system comprising:
a first layer comprising first memory cells comprising first transistors,
wherein said first transistors comprise first transistor channels;

a second layer overlying said first layer, said second layer comprising second memory cells comprising second transistors,
wherein said second transistors comprise second transistor channels,
wherein said second layer comprises vertically oriented doped regions,
wherein said second layer comprises at least one through second layer via having a diameter of less than 400 nm, and
wherein at least one of said first transistor channels and at least one of said second transistor channels are directly coupled to at least one of said vertically oriented doped regions.

2. The 3D IC based system according to claim 1 ,
wherein at least one of said vertically oriented doped regions provides a back-bias to said at least one of said first transistors.

3. The 3D IC based system according to claim 1 ,
wherein at least one of said second transistors comprises a channel region, and
wherein said at least one of said second transistors comprises a side gate and one of said vertically oriented doped regions on opposite sides of said channel region.

4. The 3D IC based system according to claim 1 ,
wherein said vertically oriented doped regions comprise polysilicon.

5. The 3D IC based system according to claim 1 ,
wherein at least one of said second memory cells forms a two stable states memory cell.

6. The 3D IC based system according to claim 1 ,
wherein at least two of said second transistors are connected by a common doped mono-crystalline structure.

7. The 3D IC based system according to claim 1 ,
wherein a first portion of at least one of said first transistors is self-aligned to a second portion of at least one of said second transistors.

8. A 3D IC based system, comprising:
a first layer comprising first memory cells comprising first transistors,
wherein said first transistors comprise first transistor channels;

a second layer overlying said first layer, said second layer comprising second memory cells comprising second transistors,
wherein said second transistors comprise second transistor channels,
wherein said second layer comprises vertically oriented doped regions,
wherein at least one of said vertically oriented doped regions provides a bias to at least one of said first transistor channels and to at least one of said second transistor channels.

9. The 3D IC based system according to claim 8 ,
wherein at least one of said second memory cells forms a two stable states memory cell.

10. The 3D IC based system according to claim 8 ,
wherein at least one of said second transistors comprises a channel region, and
wherein said at least one of said second transistors comprises a side gate and one of said vertically oriented doped regions on opposite sides of said channel region.

11. The 3D IC based system according to claim 8 ,
wherein said vertically oriented doped regions comprise polysilicon.

12. The 3D IC based system according to claim 8 ,
wherein at least one of said vertically oriented doped regions provides a back-bias to said at least one of said first transistors.

13. The 3D IC based system according to claim 8 ,
wherein at least two of said second transistors are connected by a common doped mono-crystalline structure.

14. The 3D IC based system according to claim 8 ,
wherein a first portion of at least one of said first transistors is self-aligned to a second portion of at least one of said second transistors.

15. A 3D IC based system, comprising:
a first layer comprising first memory cells comprising first transistors;
a second layer overlying said first layer, said second layer comprising second memory cells comprising second transistors; and
a third layer overlaying said second layer and comprising third transistors,
wherein at least one of said first transistors and at least one of said second transistors are connected to at least one of said third transistors, and
wherein said third transistor is connected as an output buffer.

16. The 3D IC based system according to claim 15 ,
wherein a first portion of at least one of said first transistors is self-aligned to a second portion of at least one of said second transistors.

17. The 3D IC based system according to claim 15 ,
wherein a first portion of at least one of said second transistors is self-aligned to a second portion of at least one of said third transistors.

18. The 3D IC based system according to claim 15 ,
wherein at least one of said second memory cells forms a two stable states memory cell.

19. The 3D IC based system according to claim 15 ,
wherein at least one of said second transistors and one of said first transistors share a back-bias region.

20. The 3D IC based system according to claim 15 ,
wherein at least two of said second transistors are connected by a common doped mono-crystalline structure.

Assignees

• Monolithic 3D Inc

Inventors

• Or-Bach Zvi
• Widjaja Yuniarto

Classifications

• G11C11/404 Primary

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• H01L29/7841

  Electricity · mapped topic

• H01L27/115

  Electricity · mapped topic