Distributed serialized data buffer and a memory module for a cascadable and extended memory subsystem

Patent metadata

Field	Value
Publication number	US-10102884-B2
Application number	US-201514920610-A
Country	US
Kind code	B2
Filing date	Oct 22, 2015
Priority date	Oct 22, 2015
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

Embodiments disclosed herein generally relate to techniques for routing data through one or more cascaded memory modules. Each memory module can include a plurality of data buffers. Each data buffer includes a plurality of ports for routing data to and/or from other memory modules. In one embodiment, the data buffer is configured to route write data to DRAM devices on a first memory module or route write data to a data buffer of at least one downstream memory module. The data buffer is also configured to receive read data from a DRAM device of the first memory module or receive read data from a downstream memory module.

First claim

What is claimed is:

1. A memory module in between an upstream memory module of a plurality of cascaded memory modules and a downstream memory module of the plurality of cascaded memory modules in a computing system, the memory module comprising:
a plurality of dynamic random access memory (DRAM) devices;
a command buffer configured to receive a set of commands to access data at one or more memory locations of the DRAM devices on the memory module or DRAM devices on the downstream memory module in the computing system; and
a plurality of data buffers, each different from the command buffer, wherein each data buffer is configured to:
after receiving, via a first port of the data buffer, serialized write data for a first command of the set of commands, route the serialized write data for the first command to a data buffer of the downstream memory module via a second port of the data buffer;
receive, via the first port of the data buffer, serialized write data for a second command of the set of commands;
after de-serializing the serialized write data for the second command, route the de-serialized write data to a DRAM device on the memory module;
after receiving serialized read data, in response to a third command of the set of commands, from the downstream memory module via a third port of the data buffer, route the serialized read data to the upstream memory module via a fourth port of the data buffer;
receive, in response to a fourth command of the set of commands, de-serialized read data from a DRAM device on the memory module; and
after serializing the de-serialized read data, route the serialized read data for the fourth command to the upstream memory module via the fourth port of the data buffer.

2. The memory module of claim 1 , wherein the command buffer is configured to generate, from one of the commands:
a DRAM command to control operation of a DRAM device on the memory module; and
a data buffer command, different from the DRAM command, to control operation of the data buffers, wherein the data buffer command controls routing of data, in response to the DRAM command, within the data buffers to avoid queueing of the data within the data buffers.

3. The memory module of claim 2 , wherein the command buffer is configured to generate the data buffer command based on a reduced set of commands relative to the commands in the set of commands.

4. The memory module of claim 2 , wherein the command buffer is configured to generate the data buffer command by deleting at least some information from the one of the commands, wherein the information comprises at least one of an address of a DRAM device on the memory module associated with the DRAM command or a memory operation for a DRAM device associated with the DRAM command.

5. The memory module of claim 2 , wherein the command buffer is further configured to apply a time delay to the data buffer command to account for a time delay in routing the read data and write data.

6. A method for routing data by a memory module of a plurality of cascaded memory modules in a computing system, the method comprising:
receiving, by a command buffer of the memory module, a set of commands to access data at one or more memory locations of dynamic random access memory (DRAM) devices on the memory module or at least one downstream memory module of the plurality of cascaded memory modules in the computing system, wherein the memory module is between an upstream memory module of the plurality of cascaded memory modules and the at least one downstream memory module;
after receiving, via a first port of a data buffer of a plurality of data buffers of the memory module, serialized write data for a first command of the set of commands, routing the serialized write data for the first command to a data buffer of the downstream memory module via a second port of the data buffer;
receiving, via the first port of the data buffer, serialized write data for a second command of the set of commands;
after de-serializing the serialized write data for the second command, routing the de-serialized write data to a DRAM device on the memory module;
after receiving serialized read data, in response to a third command of the set of commands, from the downstream memory module via a third port of the data buffer, routing the serialized read data to the upstream memory module via a fourth port of the data buffer;
receive, in response to a fourth command of the set of commands, de-serialized read data from a DRAM device on the memory module; and
after serializing the de-serialized read data, routing the serialized read data for the fourth command to the upstream memory module via the fourth port of the data buffer, wherein the data buffer is different from the command buffer.

7. The method of claim 6 , further comprising generating, from one of the commands:
a DRAM command to control operation of a DRAM device on the memory module; and
a data buffer command, different from the DRAM command, to control operation of the data buffers, wherein the data buffer command controls routing of data, in response to the DRAM command, within the data buffers to avoid queuing of the data within the data buffers.

8. The method of claim 7 , wherein the data buffer command is generated based on a reduced set of commands relative to the commands in the set of commands.

9. The method of claim 7 , wherein the data buffer command is generated by deleting at least some information from the one of the commands, wherein the information comprises at least one of an address of a DRAM device on the memory module associated with the DRAM command or a memory operation for a DRAM device associated with the DRAM command.

10. The method of claim 7 , further comprising applying a time delay to the data buffer command to account for a time delay in routing the read data and write data.

11. A memory system, comprising:
a plurality of cascaded memory modules, each comprising:
a plurality of dynamic random access memory (DRAM) devices;
a command buffer configured to receive a set of commands to access data at one or more memory locations of the DRAM devices on the memory module or DRAM devices on at least one downstream memory module; and
a plurality of data buffers, each different from the command buffer, wherein each data buffer is configured to:
after receiving, via a first port of the data buffer, serialized write data for a first command of the set of commands, to route the serialized write data for the first command to a data buffer of the downstream memory module via a second port of the data buffer;
receive, via the first port of the data buffer, serialized write data for a second command of the set of commands;
after de-serializing the serialized write data for the second command, route the de-serialized write data to a DRAM device on the memory module;
after receiving serialized read data, in response to a third command of the set of commands, from the downstream memory module via a third port of the data buffer, route the serialized read data to a fourth port of the data buffer;
receive, in response to a fourth command of the set of commands, de-serialized read data from a DRAM device on the memory module; and
route the serialized read data for the fourth command to the fourth port.

12. The memory system of claim 11 , wherein each memory module is coupled with at least one of:
an upstream memory module via the third and fourth ports; or
a downstream memory module via the first and second ports.

13. The memory system of claim 11 , further comprising an additional module comprising:
one or more optical transceivers for sending data to and rece

Assignees

• IBM

Inventors

• Coteus Paul W
• Dreps Daniel M
• Kilmer Charles A
• Kim Kyu-Hyoun
• Maule Warren E
• Takken Todd E

Classifications

• G11C7/109

  Control signal input circuits · CPC title

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title