Package-on-package options with multiple layer 3-d stacking

Patent metadata

Field	Value
Publication number	US-2016013156-A1
Application number	US-201414541228-A
Country	US
Kind code	A1
Filing date	Nov 14, 2014
Priority date	Jul 14, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

In some embodiments, a semiconductor device package on package assembly may include a first package, a second package, and a third package. The first package may include a first surface, a second surface, a first die, and a first set of electrical conductors. The first set of electrical conductors may be configured to electrically connect the package on package assembly. The second package may include a third surface and a fourth surface, and a local memory module. The third surface may be coupled to the second surface. The first package may be electrically coupled to the second package. The third package may include a fifth surface and a sixth surface, and a main memory module. The fifth surface may be coupled to the fourth surface. The third package may be electrically coupled to the first package and/or the second package.

First claim

1 - 8 . (canceled)

9 . A method for forming a semiconductor device package on package assembly, comprising:
forming a first package comprising a first surface, a second surface substantially opposite the first surface, a first die, and a first set of electrical conductors coupled to the first surface; forming a second package comprising a third surface and a fourth surface substantially opposite the third surface, and a local memory module, wherein the third surface is coupled to the second surface; forming a third package comprising a fifth surface and a sixth surface substantially opposite the fifth surface, and a main memory module, wherein the fifth surface is coupled to the fourth surface; electrically coupling the package on package assembly; electrically coupling the first package to the second package; and electrically coupling the third package to the first package and/or the second package; managing a first set of data using the local memory module; and managing a second set of data using the main memory module greater in size than the first set of data, and wherein the second set of data comprises at least the first set of data or a version of the first set of data.

10 . The method of claim 9 , wherein the local memory and the main memory comprise different types of memory.

11 . The method of claim 9 , wherein the local memory comprises a cache.

12 . The method of claim 9 , further comprising managing data associated with the assembly using the local memory.

13 . The method of claim 9 , further comprising managing at least data associated with a system to which the assembly is electrically coupled using the main memory.

14 . The method of claim 9 , wherein the local memory has a lower latency than the main memory.

15 . The method of claim 9 , wherein the local memory has a greater rate of data transfer than the main memory.

16 . The method of claim 9 , further comprising:
managing a data flow to and from the local memory using a first controller; and managing a data flow to and from the main memory using a second controller, wherein the second controller is different from the first controller.

17 . A method for forming a semiconductor device package on package assembly, comprising:
forming a first package comprising a first surface, a second surface substantially opposite the first surface, a first die, and a first set of electrical conductors coupled to the first surface; forming a second package comprising a third surface and a fourth surface substantially opposite the third surface, and a local memory module, wherein the third surface is coupled to the second surface; forming a third package comprising a fifth surface and a sixth surface substantially opposite the fifth surface, and a main memory module, wherein the fifth surface is coupled to the fourth surface; electrically coupling the package on package assembly; electrically coupling the first package to the second package; and electrically coupling the third package to the first package and/or the second package; managing a first set of data using the local memory module; and managing a second set of data greater in size than the first set of data using the main memory module, and wherein the local memory has a lower latency than the main memory.

18 . The method of claim 17 , wherein the local memory has a greater rate of data transfer than the main memory.

19 . The method of claim 17 , further comprising:
managing a data flow to and from the local memory using a first controller; and managing a data flow to and from the main memory using a second controller, wherein the second controller is different from the first controller.

20 . The method of claim 17 , wherein the local memory comprises a cache.

21 . The method of claim 17 , wherein the local memory and the main memory comprise different types of memory.

22 . The method of claim 17 , further comprising managing data associated with the assembly using the local memory.

23 . The method of claim 17 , further comprising managing at least data associated with a system to which the assembly is electrically coupled using the main memory.

24 . The method of claim 17 , wherein the second set of data comprises at least the first set of data.

Assignees

• Apple Inc

Inventors

• Zhai Jun
• Hu Kunzhong
• Zhong Chonghua

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title