Hybrid-integrated photonic chip package with an interposer

Patent metadata

Field	Value
Publication number	US-9297971-B2
Application number	US-201314047978-A
Country	US
Kind code	B2
Filing date	Oct 7, 2013
Priority date	Apr 26, 2013
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are proximate to each other in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a top surface of an interposer, and this top surface is in turn electrically coupled to a front surface of an input/output (I/O) integrated circuit that faces the top surface. Furthermore, the front surface of the I/O integrated circuit is electrically coupled to a top surface of the optical integrated circuit, where the top surface of the optical integrated circuit faces the front surface of the I/O integrated circuit.

First claim

What is claimed is:

1. A chip package, comprising:
an integrated circuit having a front surface with integrated-circuit connector pads;
integrated-circuit electrical connectors electrically coupled to the integrated-circuit connector pads;
an interposer having a top surface, facing the front surface of the integrated circuit, with first interposer connector pads, electrically coupled to the integrated-circuit electrical connectors, and second interposer connector pads;
input/output (I/O)-integrated-circuit electrical connectors electrically coupled to the second interposer connector pads;
an I/O integrated circuit having a front surface, facing the top surface, with first I/O-integrated-circuit connector pads electrically coupled to the I/O-integrated-circuit electrical connectors, and second I/O-integrated-circuit connector pads, wherein the I/O integrated circuit is proximate to the integrated circuit on a same side of the interposer, and wherein the I/O integrated circuit includes electrical I/O circuits and optical driver and receiver circuits;
optical-integrated-circuit electrical connectors electrically coupled to the second I/O-integrated-circuit connector pads; and
an optical integrated circuit having a top surface, facing the front surface of the I/O integrated circuit, with optical-integrated-circuit connector pads electrically coupled to the optical-integrated-circuit electrical connectors, wherein the optical integrated circuit is configured to communicate optical signals;
wherein the optical integrated circuit is placed adjacent to the interposer, and wherein a part of the I/O integrated circuit extends beyond an edge of the interposer to dispose on top of the optical integrated circuit.

2. The chip package of claim 1 , wherein the integrated circuit is adjacent to the I/O integrated circuit.

3. The chip package of claim 1 , wherein the interposer further includes:
third interposer connector pads disposed on a bottom surface on an opposite side of the interposer from the top surface; and
through-substrate vias (TSVs) electrically coupling the first interposer connector pads to the third interposer connector pads, and the second interposer connector pads to the third interposer connector pads.

4. The chip package of claim 3 , wherein the TSVs are configured to convey power and ground to the integrated circuit and the I/O integrated circuit.

5. The chip package of claim 3 , wherein the chip package further includes:
substrate electrical connectors electrically coupled to the third interposer connector pads; and
a substrate having a front surface electrically coupled to the substrate electrical connectors.

6. The chip package of claim 5 , wherein the chip package further includes a ramp-stack chip package electrically coupled to a back surface on an opposite side of the substrate from the top surface, and
wherein the ramp-stack chip package includes multiple parallel substrates arranged at an oblique angle relative to the back surface.

7. The chip package of claim 5 , wherein a back surface of the optical integrated circuit on an opposite side of the optical integrated circuit from the top surface of the optical integrated circuit is coupled to the front surface of the substrate.

8. The chip package of claim 1 , wherein the chip package further includes a second interposer between the front surface of the substrate and a bottom surface of the interposer on an opposite side of the interposer from the front surface of the interposer.

9. The chip package of claim 1 , wherein the chip package further includes an optical fiber edge coupled to the optical integrated circuit.

10. The chip package of claim 9 , wherein the optical fiber is coupled to one of: the top surface of the optical integrated circuit; and a back surface of the optical integrated circuit on an opposite side of the optical integrated circuit from the top surface of the optical integrated circuit.

11. The chip package of claim 1 , wherein the chip package further includes an optical fiber vertically coupled to the optical integrated circuit.

12. The chip package of claim 11 , wherein the optical fiber is coupled to one of: the top surface of the optical integrated circuit; and a back surface of the optical integrated circuit on an opposite side of the optical integrated circuit from the top surface of the optical integrated circuit.

13. The chip package of claim 1 , wherein the chip package further includes an optical source optically coupled to the optical integrated circuit.

14. The chip package of claim 1 , wherein the interposer includes one of: a ceramic, an organic material, a glass, and a semiconductor.

15. The chip package of claim 1 , wherein the chip package further includes a thermal-cooling mechanism on a back surface of the integrated circuit on an opposite side of the integrated circuit from the front surface of the integrated circuit.

16. A system, comprising:
a processor;
a memory coupled to the processor; and
a chip package, wherein the chip package includes:
an integrated circuit having a front surface with integrated-circuit connector pads;
integrated-circuit electrical connectors electrically coupled to the integrated-circuit connector pads;
an interposer having a top surface, facing the front surface of the integrated circuit, with first interposer connector pads, electrically coupled to the integrated-circuit electrical connectors, and second interposer connector pads;
input/output (I/O)-integrated-circuit electrical connectors electrically coupled to the second interposer connector pads;
an I/O integrated circuit having a front surface, facing the top surface, with first I/O-integrated-circuit connector pads electrically coupled to the I/O-integrated-circuit electrical connectors, and second I/O-integrated-circuit connector pads, wherein the I/O integrated circuit is proximate to the integrated circuit on a same side of the interposer, and wherein the I/O integrated circuit includes electrical I/O circuits and optical driver and receiver circuits;
optical-integrated-circuit electrical connectors electrically coupled to the second I/O-integrated-circuit connector pads; and
an optical integrated circuit having a top surface, facing the front surface of the I/O integrated circuit, with optical-integrated-circuit connector pads electrically coupled to the optical-integrated-circuit electrical connectors, wherein the optical integrated circuit is configured to communicate optical signals;
wherein the optical integrated circuit is placed adjacent to the interposer, and wherein a part of the I/O integrated circuit extends beyond an edge of the interposer to dispose on top of the optical integrated circuit.

17. The system of claim 16 , wherein the interposer further includes:
third interposer connector pads disposed on a bottom surface on an opposite side of the interposer from the top surface; and
through-substrate vias (TSVs) electrically coupling the first interposer connector pads to the third interposer connector pads, and the second interposer connector pads to the third interposer connector pads.

18. The system of claim 17 , wherein the chip package further includes:
substrate electrical connectors electrically coupled to the third interposer connector pads; and
a substrate having a front surface electrically coupled to the substrate electrical connectors.

19. The system of claim 18 , wherein the chip package further includes a ramp-stack chip package electrically coupled to a back surface on an opposite side

Assignees

• Oracle Int Corp

Inventors

• Thacker Hiren D
• Krishnamoorthy Ashok V
• Hopkins Ii Robert David
• Lexau Jon
• Zheng Xuezhe
• Ho Ronald
• Shubin Ivan
• Cunningham John E

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/295

  optical coupling · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title