Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11646305-B2
Application number	US-202016946620-A
Country	US
Kind code	B2
Filing date	Jun 30, 2020
Priority date	Oct 2, 2019
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

Semiconductor devices may include standard cells arranged in a first direction and a second direction intersecting the first direction. Both the first and second directions may be parallel to an upper surface of the substrate. Each of the standard cells may include semiconductor elements. The semiconductor device may also include filler cells between two standard cells, and each of the filler cells may include a filler active region and a filler contact connected to the filler active region and may extend in the first direction. The semiconductor device may further include a lower wiring pattern electrically connected to at least one of the semiconductor elements and may extend into at least one of the filler cells in the second direction, and the filler contacts may include wiring filler contacts lower than the lower wiring pattern and connected to at least one of the lower wiring pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
standard cells arranged in a first direction and a second direction on a substrate, wherein both the first direction and the second direction are parallel to an upper surface of the substrate, and the second direction is intersecting the first direction, and wherein each of the standard cells includes semiconductor elements and a lower wiring pattern that is electrically connected to at least one of the semiconductor elements and extends in the second direction; and
filler cells on the substrate, wherein each of the filler cells is between two standard cells of the standard cells adjacent to each other in the second direction and includes a filler active region and a filler contact that is connected to the filler active region and extends in the first direction,
wherein the filler cells include a first filler cell between a first standard cell and a second standard cell of the standard cells adjacent to each other in the second direction, and
the lower wiring pattern of the first standard cell extends into the first filler cell and is connected to the filler contact of the first filler cell, and a lowermost surface of the filler contact of the first filler cell is above the substrate, and an uppermost surface of the filler contact of the first filler cell is below the lower wiring pattern of the first standard cell.

2. The semiconductor device of claim 1 , wherein the standard cells include a third standard cell and a fourth standard cell adjacent to each other in the second direction, and the filler cells include a second filler cell between the third and fourth standard cells, and
wherein the filler contact of the second filler cell includes a dummy filler contact that is spaced apart from the lower wiring patterns of the first, second, third, and fourth standard cells.

3. The semiconductor device of claim 2 ,
wherein the standard cells include a fifth standard cell and a sixth standard cell adjacent to each other in the second direction, and the filler cells include a third filler cell between the fifth and sixth standard cells,
wherein the filler contact of the first filler cell includes first wiring filler contacts, and each of the first wiring filler contacts is connected to at least one of the lower wiring patterns of the first, second, third, fourth, fifth, and sixth standard cells,
the filler contact of the second filler cell includes a second wiring filler contact that is connected to at least one of the lower wiring patterns of the first, second, third, fourth, fifth, and sixth standard cells and a second dummy filler contact that is spaced apart from the lower wiring patterns of the first, second, third, fourth, fifth, and sixth standard cells, and
the third filler cell includes third dummy filler contacts that are spaced apart from the lower wiring patterns of the first, second, third, fourth, fifth, and sixth standard cells.

4. The semiconductor device of claim 3 , wherein the first wiring filler contacts included in the first filler cell have different lengths in the first direction.

5. The semiconductor device of claim 3 , wherein the second wiring filler contact and the second dummy filler contact included in the second filler cell have an equal length in the first direction.

6. The semiconductor device of claim 3 , wherein the third dummy filler contacts included in the third filler cell have an equal length in the first direction.

7. The semiconductor device of claim 3 , wherein at least one of the first wiring filler contacts included in the first filler cell is electrically connected to the lower wiring patterns extending from two standard cells of the standard cells, and the two standard cells of the standard cells are not aligned in the first direction and the second direction.

8. The semiconductor device of claim 3 , wherein at least one of the first wiring filler contacts included in the first filler cell is electrically connected to the lower wiring patterns extending from two standard cells of the standard cells, and the two standard cells of the standard cells are not aligned in the first direction and are aligned in the second direction.

9. The semiconductor device of claim 3 , wherein the second wiring filler contact included in the second filler cell is electrically connected to the lower wiring patterns extending from two standard cells of the standard cells, and the two standard cells of the standard cells are not aligned in the first direction and are aligned in the second direction.

10. The semiconductor device of claim 1 , further comprising:
at least one via structure connecting one of the filler contacts with one of the lower wiring patterns.

11. The semiconductor device of claim 1 , wherein the filler contacts and the lower wiring patterns include different conductive materials.

12. The semiconductor device of claim 1 , further comprising:
at least one contact separation region separating two filler contacts that are aligned in the first direction.

13. The semiconductor device of claim 12 , wherein the at least one contact separation region includes a first contact separation region that is spaced apart from power wiring patterns in the first direction, and each of the power wiring patterns is on a respective boundary between two filler cells of the filler cells adjacent to each other in the first direction.

14. The semiconductor device of claim 13 , wherein the at least one contact separation region further includes a second contact separation region different from the first contact separation region, and the second contact separation region is disposed below at least one of the power wiring patterns.

15. A semiconductor device, comprising:
a standard cell region and a filler cell region adjacent to each other in a first direction that is parallel to an upper surface of a substrate;
at least one semiconductor element in the standard cell region;
at least one dummy element and a filler contact in the filler cell region;
a lower wiring pattern above the least one semiconductor element and continuously extending from the standard cell region into the filler cell region in the first direction, the lower wiring pattern comprising a portion in the filler cell region; and
a via structure in the filler cell region, wherein an uppermost surface of the via structure is below the portion of the lower wiring pattern, and a lowermost surface of the via structure is above the filler contact, and the via structure is in contact with the portion of the lower wiring pattern and is in contact with the filler contact.

16. The semiconductor device of claim 15 ,
wherein the filler contact of the filler cell region includes a wiring filler contact in contact with the via structure and a dummy filler contact spaced apart from the via structure; and
wherein the dummy filler contact intersects the at least one lower wiring pattern in the filler cell region.

17. The semiconductor device of claim 16 , wherein the wiring filler contact and the dummy filler contact have different lengths in a second direction that intersects the first direction.

18. The semiconductor device of claim 16 , wherein the wiring filler contact is connected to a second lower wiring pattern different from the at least one lower wiring pattern.

19. A semiconductor device, comprising:
first and second standard cells on a substrate, wherein each of the first and second standard cells includes a semiconductor element and a lower wiring pattern electrically connected to the semicondu

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sungok
• Park Sangdo
• Seomun Jun
• Lee Bonghyun

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• H10D84/975

  Wiring regions or routing · CPC title