Line cut patterning using sacrificial material

Patent metadata

Field	Value
Publication number	US-11527434-B2
Application number	US-202016796079-A
Country	US
Kind code	B2
Filing date	Feb 20, 2020
Priority date	Feb 20, 2020
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate, the first line pattern having a pitch defined by a target line width and a minimum width of space between lines;
forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines so that a combined dimension of the target line width and the width of the spacer ranges from 10 nm to 50 nm, wherein the forming the first spacer minimizes pinch points and provides a first gap having the target line width;
forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer;
forming a line cut at a second location above the at least one hard mask;
forming, within the line cut, a second plug corresponding to the second location and including second sacrificial cut material to block pattern transfer into the at least one hard mask layer; and
removing material up to the first and second plugs to form a third gap.

2. The method of claim 1 , further comprising patterning the first sacrificial mandrel material to form the first line pattern.

3. The method of claim 1 , wherein the first plug is a negative tone plug.

4. The method of claim 1 , wherein the at least one hard mask layer includes a first hard mask layer and a second hard mask layer.

5. The method of claim 4 , wherein the first hard mask layer includes titanium nitride and the second hard mask layer includes silicon nitride.

6. The method of claim 1 , wherein the first plug includes first sacrificial cut material, and further comprising:
forming second sacrificial mandrel material above the first plug, the first spacer and the first sacrificial mandrel material;
forming a second line pattern having the pitch within the second sacrificial mandrel material;
forming, within the second line pattern, a second spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a second gap having the target line width; and
etching back the second spacer to form a second gap having the target line width.

7. The method of claim 6 , wherein the removing material up to the first and second plugs to the at least one hard mask layer to form a third gap.

8. The method of claim 7 , further comprising performing a pattern transfer without etching the first plug.

9. The method of claim 8 , further comprising removing material above the at least one hard mask layer after performing the pattern transfer.

10. A method for fabricating a semiconductor device, comprising:
forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate, the first line pattern having a pitch defined by a target line width and a minimum width of space between lines;
forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines so that a combined dimension of the target line width and the width of the spacer ranges from 10 nm to 50 nm, wherein the forming the first spacer minimizes pinch points and provides a first gap having the target line width;
forming a first plug as a negative tone plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer; and
forming a second plug corresponding to a second location above the at least one hard mask layer.

11. The method of claim 10 , further comprising patterning the first sacrificial mandrel material to form the first line pattern.

12. The method of claim 10 , wherein the at least one hard mask layer includes a first hard mask layer including titanium nitride and a second hard mask layer including silicon nitride.

13. The method of claim 10 , further comprising:
forming second sacrificial mandrel material above the first plug, the first spacer and the first sacrificial mandrel material;
forming a second line pattern having the pitch within the second sacrificial mandrel material;
forming a second spacer within the first line pattern having a width corresponding to the minimum width of space between lines and a first gap having the target line width; and
etching back the second spacer to form a second gap having the target line width.

14. The method of claim 13 , wherein the first plug includes first sacrificial cut material, and wherein forming the second plug further includes forming a line cut at the second location, and filling the line cut with second sacrificial cut material to block pattern transfer into the at least one hard mask layer.

15. The method of claim 14 , further comprising:
removing material up to the first and second plugs and material within the second gap to the at least one hard mask layer to form a third gap; and
performing a pattern transfer without etching the first and second plugs.

16. The method of claim 15 , further comprising removing material above the at least one hard mask layer after performing the pattern transfer.

17. A method for fabricating a semiconductor device, comprising:
forming a first line pattern within sacrificial mandrel material disposed on a plurality of hard mask layers disposed on a substrate, the first line pattern having a pitch defined by a target line width and a minimum width of space between lines, and the plurality of hard mask layers including a first hard mask layer and a second hard mask layer disposed on the first hard mask layer;
forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines so that a combined dimension of the target line width and the width of the spacer ranges from 10 nm to 50 nm, wherein the forming the first spacer minimizes pinch points and provides a first gap having the target line width;
forming a first plug as a negative tone plug including first sacrificial cut material within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer;
forming second sacrificial mandrel material above the first plug, the first spacer and the first sacrificial mandrel material;
forming a second line pattern having the pitch within the second sacrificial mandrel material;
forming, within the second line pattern, a second spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a second gap having the target line width;
etching back the second spacer to form a second gap having the target line width;
forming a line cut at a second location above the at least one hard mask layer; and
forming a second plug including second sacrificial cut material within the line cut.

18. The method of claim 17 , further comprising patterning the first sacrificial mandrel material to form the first line pattern.

19. The method of claim 17 , wherein the first hard mask layer includes titanium nitride and the second hard mask layer includes silicon nitride.

20. The method of claim 17 , further comprising:
removing material up to the first and second plugs and material within the second gap to the first hard mask layer to form a third gap;
performing a pattern transfer without etching the first and second plugs; and
removing m

Assignees

• IBM

Inventors

• Philip Timothy Mathew
• Dechene Daniel James
• Ghosh Somnath
• Robison Robert

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/067

  by modifying the pattern of conductive parts · CPC title