Method for interrupting a line in an interconnect

Patent metadata

Field	Value
Publication number	US-10242907-B2
Application number	US-201715615299-A
Country	US
Kind code	B2
Filing date	Jun 6, 2017
Priority date	Jun 7, 2016
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A method for forming a pattern for an integrated circuit is disclosed. In one aspect, the method includes (a) providing a hardmask layer; (b) overlaying the hard mask layer with a set of parallel material lines delimiting gaps therebetween; and (c) providing a spacer layer following the shape of the material layer. The method further includes (d) removing a top portion of the spacer layer, thereby forming spacer lines alternatively separated by material lines and by gaps; and (e) providing a blocking element in a portion of a gap. The method also includes (f) etching selectively the hard mask layer by using the material layer, the spacer lines and the blocking element as a mask, thereby providing a first set of parallel trenches in the hardmask layer, wherein a trench has a blocked portion; and (g) selectively removing the blocking element.

First claim

What is claimed is:

1. A method of forming a pattern for an integrated circuit, comprising:
(a) providing a hardmask layer;
(b) overlaying the hard mask layer with a material layer having a shape comprising a set of parallel material lines delimiting gaps therebetween, the gaps forming a first set of gaps;
(c) providing a spacer layer following the shape of the material layer, the spacer layer thereby covering the top of the material lines;
(d) removing a top portion of the spacer layer in such a way as to expose a top surface of the material lines, thereby forming spacer lines alternatively separated by material lines and by gaps of the first set;
(e) providing a blocking element in a portion of a gap of the first set present between two spacer lines and between two material lines;
(f) etching selectively the hard mask layer by using the material layer, the spacer lines and the blocking element as a mask, thereby providing a first set of parallel trenches in the hardmask layer, wherein a trench has a blocked portion; and
(g) selectively removing the blocking element.

2. The method according to claim 1 , wherein the blocking element overlaps with the two spacer lines between which the portion of the gap is present.

3. The method according to claim 2 , wherein the two spacer lines have a width (w 1 ) and wherein the blocking element overlaps with each of the two spacer lines across their entire width (w 1 ).

4. The method according to claim 3 , wherein the blocking element further overlaps with a portion of each of the two top surfaces of the two material lines between which the portion of the gap is present.

5. The method according to claim 1 , further comprising:
(h) filling the first set of parallel trenches and the gaps of the first set with a filling material in such a way that a top surface of the filling material is coplanar with the top surface of the material lines;
(i) selectively removing the material lines, thereby forming a second set of gaps;
(j) providing a further blocking element in a portion of a gap of the second set, present between two spacer lines; and
(k) etching selectively through the hard mask layer by using the filling material and the blocking element as a mask, thereby providing a second set of parallel trenches in the hardmask layer, wherein a trench within the second set has a blocked portion.

6. The method according to claim 5 , wherein the further blocking element overlaps with the two spacer lines between which the portion of the gap of the second set is present.

7. The method according to claim 6 , wherein the two spacer lines have a width (w 1 ) and wherein the further blocking element overlaps with each of the two spacer lines across their entire width (w 1 ).

8. The method according to claim 7 , wherein the further blocking element further overlaps with a portion of the filled gaps of the first set neighboring the portion of the gap of the second set.

9. The method according to claim 1 , wherein the hardmask layer is on top of a target substrate and wherein the method further comprises a step of etching the target substrate through the hard mask layer, thereby forming trenches in the target substrate, wherein at least one trench amongst the trenches has a blocked portion.

10. The method according to claim 9 , further comprising filling the trenches in the target substrate with an electrically conductive material.

Assignees

• Imec Vzw

Inventors

• Ryckaert Julien
• Boemmels Juergen
• Wilson Christopher

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/285

  of materials not containing Si, e.g. PZT or Al2O3 · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title