Forming semiconductor fins with self-aligned patterning

Patent metadata

Field	Value
Publication number	US-9704859-B1
Application number	US-201615148052-A
Country	US
Kind code	B1
Filing date	May 6, 2016
Priority date	May 6, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A method for fabricating a semiconductor device comprises removing a portion of a substrate to form a first cavity in the substrate and depositing an insulator material in the first cavity. A sacrificial pattern is formed on a portion of the insulator material in the first cavity and the substrate. Exposed portions of the substrate are removed to form a fin in the substrate. A gate stack is formed over a portion of the fin.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
removing a portion of a substrate to form a first cavity in the substrate;
depositing an insulator material in the first cavity;
forming a sacrificial pattern on a portion of the insulator material in the first cavity and the substrate;
removing exposed portions of the substrate to form a fin in the substrate; and
forming a gate stack over a portion of the fin.

2. The method of claim 1 , wherein the forming the sacrificial pattern includes:
forming a first sacrificial layer on the substrate and the insulator material;
forming a second sacrificial layer on the first sacrificial layer;
removing portions of the second sacrificial layer to form a first sacrificial mandrel;
forming a sacrificial spacer along sidewalls of the first sacrificial mandrel;
removing the first sacrificial mandrel and exposed portions of the first sacrificial layer to form a second sacrificial mandrel; and
forming a second sacrificial spacer along sidewalls of the second sacrificial mandrel, a portion of the second sacrificial spacer arranged on the insulator material and a portion of the second sacrificial spacer arranged on the substrate.

3. The method of claim 2 , wherein the first sacrificial layer includes amorphous silicon.

4. The method of claim 2 , wherein the second sacrificial layer includes amorphous carbon.

5. The method of claim 1 , further comprising:
removing a portion of the substrate to form a second cavity in the substrate; and
depositing the insulator material in the second cavity, wherein the forming the sacrificial pattern on the portion of the insulator material in the first cavity and the substrate includes forming the sacrificial pattern on a portion of the insulator material in the second cavity.

6. The method of claim 1 , further comprising:
removing the insulator material after forming the fin in the substrate; and
depositing an insulator material layer adjacent to the fin.

7. The method of claim 6 , further comprising depositing a liner layer in the first cavity on the substrate prior to depositing the insulator material layer adjacent to the fin.

8. The method of claim 1 , further comprising:
removing the a portion of the insulator material from the first cavity to reduce a thickness of the insulator material after forming the fin in the substrate; and
depositing an insulator material layer over the insulator material in the first cavity and over the substrate adjacent to the fin.

9. The method of claim 8 , further comprising depositing a liner layer in the first cavity over the insulator material and over the substrate prior to depositing the insulator material layer.

10. The method of claim 1 , wherein the substrate includes a semiconductor material.

11. The method of claim 1 , further comprising depositing a hardmask on the substrate prior to forming the first cavity in the substrate.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Lie Fee Li
• Xu Peng

Classifications

• H10P50/696

  Process specially adapted to improve the resolution of the mask · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/242

  of Group IV materials · CPC title