Package structures and methods of forming

Patent metadata

Field	Value
Publication number	US-11444057-B2
Application number	US-202016889487-A
Country	US
Kind code	B2
Filing date	Jun 1, 2020
Priority date	Sep 5, 2014
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure. The method further includes encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant, forming a front side redistribution structure on the encapsulant, and electrically coupling a second integrated circuit die to the first integrated circuit die. The second integrated circuit die is electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first package comprising:
a first integrated circuit die having an active side and a back side opposite from the active side,
an encapsulant laterally encapsulating the first integrated circuit die, a first surface of the encapsulant being coplanar with a surface of a die connector on an active side of the first integrated circuit die, a second surface of the encapsulant being opposite from the first surface of the encapsulant,
a first redistribution structure on the first surface of the of the encapsulant,
a second redistribution structure on the second surface of the encapsulant, and
a first through via extending through the encapsulant, a first end of the through via extending into the second redistribution structure, the through via extending over a surface of the second redistribution structure facing the first redistribution structure; and

a second integrated circuit die directly coupled to the first redistribution structure through first external electrical connectors.

2. The semiconductor device of claim 1 , wherein the first external electrical connectors comprise solder.

3. The semiconductor device of claim 1 , wherein the second integrated circuit die overlaps the first integrated circuit die and the first through via in a plan view.

4. The semiconductor device of claim 1 further comprising a third integrated circuit die directly coupled to the first redistribution structure through second external connectors.

5. The semiconductor device of claim 1 , wherein the first package further comprises a third integrated circuit die, the encapsulant laterally encapsulating the third integrated circuit die.

6. The semiconductor device of claim 5 further comprising a fourth integrated circuit die directly coupled to the first redistribution structure through second external connectors, wherein the fourth integrated circuit die overlaps an outer perimeter of the third integrated circuit die in a plan view.

7. The semiconductor device of claim 6 further comprising a second through via extending through the encapsulant, wherein the fourth integrated circuit die overlaps the second through via in the plan view.

8. A semiconductor device comprising:
a first redistribution structure comprising:
a first insulating layer; and
metallization layers over the first insulating layer, each of the metallization layers being separated by one or more insulating layers;

through vias on the first redistribution structure, the through vias extending through an uppermost insulating layer of the first redistribution structure, a portion of the through vias extending over an uppermost surface of the uppermost insulating layer;
a first integrated circuit die on the first redistribution structure, a front side of the first integrated circuit die comprising a first pad and a first die connector electrically connected to the first pad;
a second integrated circuit die on the first redistribution structure, a front side of the second integrated circuit die comprising a second pad and a second die connector electrically connected to the second pad;
encapsulant around the first integrated circuit die and second integrated circuit die;
a second redistribution structure directly on the encapsulant, the through vias, the first integrated circuit die, and the second integrated circuit die, the front side of the first integrated circuit die facing the second redistribution structure, the front side of the second integrated circuit die facing the second redistribution structure; and
a third integrated circuit die directly coupled to the second redistribution structure by first external electrical connectors mechanically attached to the second redistribution structure, an active side of the third integrated circuit die facing the second redistribution structure, wherein the third integrated circuit die overlaps the first integrated circuit die.

9. The semiconductor device of claim 8 further comprising second external electrical connectors coupled to the first redistribution structure, wherein the first redistribution structure is interposed between the second external electrical connectors and the through vias.

10. The semiconductor device of claim 9 , wherein the second external electrical connectors comprise an under bump metallization and solder, wherein the under bump metallization extends through the first insulating layer to a first metallization layer of the metallization layers, wherein the under bump metallization is interposed between the solder and the first metallization layer.

11. The semiconductor device of claim 10 , wherein the under bump metallization has a first taper extending through the first insulating layer, wherein the a first metallization layer of the metallization layers has a second taper extending through a second insulating layer of the one or more insulating layers, wherein the first taper is opposite the second taper.

12. The semiconductor device of claim 8 , further comprising a fourth integrated circuit die directly coupled to the second redistribution structure by second external electrical connectors mechanically attached to the second redistribution structure, an active side of the fourth integrated circuit die facing the second redistribution structure.

13. The semiconductor device of claim 12 , wherein a thickness of the third integrated circuit die is greater than a thickness of the fourth integrated circuit die.

14. The semiconductor device of claim 13 , wherein the fourth integrated circuit die overlaps the second integrated circuit die.

15. A semiconductor device comprising:
a first redistribution structure comprising:
a first insulating layer;
a first metallization layer;
a second metallization layer, wherein the first metallization layer is interposed between the second metallization layer and the first insulating layer; and
a second insulating layer, wherein the second metallization layer is interposed between the second insulating layer and the first metallization layer;

a through via on the first redistribution structure, a portion of the through via extending through the second insulating layer to the second metallization layer;
a first integrated circuit die on the first redistribution structure;
encapsulant around the first integrated circuit die and the through via, wherein a top surface of the through via, a top surface of the encapsulant, and the top surface of the first integrated circuit die are level;
a second redistribution structure on the encapsulant, an active side of the first integrated circuit die facing the second redistribution structure;
a second integrated circuit die directly attached to the second redistribution structure by a first external electrical connector, wherein the second integrated circuit die at least partially overlaps the first integrated circuit die; and
a second external electrical connector extending through the first insulating layer.

16. The semiconductor device of claim 15 further comprising:
a third integrated circuit die, wherein the encapsulant encapsulates the third integrated circuit die; and
a fourth integrated circuit die directly attached to the second redistribution structure by a second external electrical connector.

17. The semiconductor device of claim 16 , wherein the fourth integrated circuit die overlaps the third integrated circuit die.

18. The semiconductor device of claim 15 , wherein sidewalls of the second external electrical connector and sidewalls of the through via extending through th

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Yeh Der-Chyang
• Chen Hsien-Wei

Classifications

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title