Embedded component device and manufacturing methods thereof

Patent metadata

Field	Value
Publication number	US-9406658-B2
Application number	US-97204610-A
Country	US
Kind code	B2
Filing date	Dec 17, 2010
Priority date	Dec 17, 2010
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening.

First claim

What is claimed is:

1. An embedded component device, comprising:
an electronic component including an electrical contact;
an upper patterned conductive layer;
a single dielectric layer between the upper patterned conductive layer and the electronic component, the dielectric layer having a first opening exposing the electrical contact;
a first electrical interconnect extending from the electrical contact to the upper patterned conductive layer, wherein the first electrical interconnect fills the first opening;
a lower patterned conductive layer embedded in the dielectric layer, the dielectric layer having a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer, the second opening having an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer;
a conductive via located at the lower portion of the second opening; and
a second electrical interconnect filling the upper portion of the second opening;
wherein the second electrical interconnect includes a top surface having a first area, and includes a bottom surface having a second area, and the first area is different from the second area; and
wherein the conductive via includes an upper surface having a third area substantially parallel to the second area, and the third area is larger than the second area.

2. The embedded component device of claim 1 , wherein the upper patterned conductive layer is electrically connected to the lower patterned conductive layer on a conductive path including the conductive via and the second electrical interconnect.

3. The embedded component device of claim 1 , wherein the conductive via is a plated conductive post.

4. The embedded component device of claim 1 , wherein a first distance from the upper surface of the conductive via to the upper patterned conductive layer is less than a second distance from an upper surface of the electronic component to the upper patterned conductive layer.

5. The embedded component device of claim 1 , wherein the electronic component is at least one of an active component and a passive component.

6. The embedded component device of claim 1 , wherein the dielectric layer includes at least one of a prepreg layer, a resin layer, and an epoxy layer.

7. The embedded component device of claim 6 , wherein the dielectric layer includes fiber, and portions of the fiber are oriented away from the lower patterned conductive layer.

8. The embedded component device of claim 1 , wherein the electronic component has a back surface, the back surface being disposed adjacent to the lower patterned conductive layer.

9. The embedded component device of claim 1 , wherein the upper surface of the conductive via is substantially coplanar with an active surface of the electronic component.

10. An embedded component device, comprising:
an upper patterned conductive layer;
a lower patterned conductive layer;
an electronic component electrically connected to at least one of the upper patterned conductive layer and the lower patterned conductive layer;
a single dielectric layer between the upper patterned conductive layer and the lower patterned conductive layer and encapsulating the electronic component, the dielectric layer defining an opening extending from the lower patterned conductive layer to the upper patterned conductive layer, the lower patterned conductive layer embedded in the single dielectric layer;
a conductive via located at a lower portion of the opening and electrically connected to the lower patterned conductive layer; and
an electrical interconnect located at an upper portion of the opening and electrically connected to the upper patterned conductive layer;
wherein the electrical interconnect includes a top surface having a first area, and includes a bottom surface having a second area, and the first area is different from the second area; and
wherein the conductive via includes an upper surface having a third area substantially parallel to the second area, and the third area is larger than the second area.

11. The embedded component device of claim 10 , wherein the upper patterned conductive layer is electrically connected to the lower patterned conductive layer on a conductive path including the conductive via and the electrical interconnect.

12. The embedded component device of claim 10 , wherein the conductive via is a conductive post.

13. The embedded component device of claim 10 , wherein the first area is larger than the second area.

14. An embedded component device, comprising:
a first dielectric layer defining a cavity;
a lower patterned conductive layer disposed over the first dielectric layer;
an electronic component disposed in the cavity defined by the first dielectric layer;
a second dielectric layer encapsulating the electronic component, the second dielectric layer defining an opening extending through the second dielectric layer, the lower patterned conductive layer embedded in the second dielectric layer;
an upper patterned conductive layer disposed over the second dielectric layer;
a conductive via located at a lower portion of the opening and electrically connected to the lower patterned conductive layer; and
an electrical interconnect located at an upper portion of the opening and electrically connected to the upper patterned conductive layer;
wherein the electrical interconnect includes a top surface having a first area, and includes a bottom surface having a second area, and the first area is different from the second area; and
wherein the conductive via includes an upper surface having a third area substantially parallel to the second area, and the third area is larger than the second area.

15. The embedded component device of claim 14 , wherein an upper surface of the electronic component is recessed below an upper surface of the second dielectric layer.

16. The embedded component device of claim 14 , wherein an active surface of the electronic component faces the upper patterned conductive layer.

Assignees

• Lee Chun-Che
• Su Yuan-Chang
• Lee Ming Chiang
• Huang Shih-Fu
• Advanced Semiconductor Eng

Inventors

• Lee Chun-Che
• Su Yuan-Chang
• Lee Ming Chiang
• Huang Shih-Fu

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title