Fan-out interconnect structure and methods forming the same

US9659805B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9659805-B2
Application numberUS-201514690015-A
CountryUS
Kind codeB2
Filing dateApr 17, 2015
Priority dateApr 17, 2015
Publication dateMay 23, 2017
Grant dateMay 23, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: forming an adhesive layer over a carrier; forming a blanket layer as a sacrificial layer over the adhesive layer, wherein the carrier and the sacrificial layer are in contact with opposite surfaces of the adhesive layer; forming through-vias overlapping the sacrificial layer; placing a device die over the sacrificial layer; molding the device die in an encapsulating material; planarizing top surfaces of the device, the through-vias, and the encapsulating material to form a planar top surface; de-bonding the carrier by removing the adhesive layer; and removing the sacrificial layer from a combined structure comprising the device die, the through-vias, and the encapsulating material. 2. The method of claim 1 , wherein the forming the sacrificial layer comprises forming a hexamethyldisilance (HMDS) layer. 3. The method of claim 2 , wherein the removing the sacrificial layer is performed by a same step as the de-bonding the carrier. 4. The method of claim 1 , wherein the forming the sacrificial layer comprises forming a metal layer or an inorganic dielectric layer. 5. The method of claim 1 , wherein the removing the sacrificial layer comprises etching an entirety of the sacrificial layer. 6. The method of claim 4 , wherein the forming the sacrificial layer comprises forming a titanium layer. 7. The method of claim 4 , wherein the forming the sacrificial layer comprises forming an oxide layer. 8. The method of claim 1 further comprising: before the forming the through-vias, forming and patterning a dielectric layer over the sacrificial layer, with portions of the sacrificial layer exposed through openings in the dielectric layer; and forming a metal seed layer over the sacrificial layer and plating the through-vias starting from the metal seed layer, wherein the metal seed layer extends into the openings in the dielectric layer. 9. The method of claim 1 , wherein the forming the through-vias comprises: forming a metal seed layer over the sacrificial layer; and plating the through-vias starting from the metal seed layer, wherein an entirety of the metal seed layer is formed as a planar layer. 10. The method of claim 1 , wherein the sacrificial layer is formed over the adhesive layer after the adhesive layer is formed over the carrier. 11. A method comprising: forming an adhesive layer over a carrier; forming a sacrificial layer over the adhesive layer; forming a dielectric layer over the sacrificial layer; patterning the dielectric layer to allow portions of the sacrificial layer exposed through openings in the dielectric layer; forming a metal seed layer over the sacrificial layer, wherein the metal seed layer extends into the openings in the dielectric layer; forming through-vias over the sacrificial layer, wherein the through-vias are plated from the metal seed layer; placing a device die over the sacrificial layer; molding and planarizing the device die and the through-vias; de-bonding the carrier by removing the adhesive layer; and removing the sacrificial layer. 12. The method of claim 11 , wherein the forming the sacrificial layer comprises forming an organic layer. 13. The method of claim 11 , wherein the removing the sacrificial layer is performed by a same step as the de-bonding the carrier. 14. The method of claim 11 , wherein the forming the sacrificial layer comprises forming a metal layer or an inorganic dielectric layer. 15. The method of claim 11 , wherein in the removing the sacrificial layer, an entirety of the sacrificial layer is removed. 16. The method of claim 11 , wherein the sacrificial layer is removed after the de-bonding the carrier. 17. The method of claim 11 , wherein the forming the sacrificial layer comprises forming an oxide layer. 18. The method of claim 11 , wherein the removing the sacrificial layer comprises etching. 19. The method of claim 11 , wherein the sacrificial layer is a substantially planar layer. 20. The method of claim 1 , wherein a portion of the sacrificial layer overlaps both a portion of the adhesive layer and a portion of the carrier.

Assignees

Inventors

Classifications

  • the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer · CPC title

  • Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

  • of die-attach connectors · CPC title

  • On different surfaces · CPC title

  • on encapsulations · CPC title

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Frequently asked questions

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What does patent US9659805B2 cover?
A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P72/74. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 23 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).