Semiconductor devices and methods of manufacturing
US-12166025-B2 · Dec 10, 2024 · US
used to support a device or a wafer when forming electrical connections thereto
used to support a device or a wafer when forming electrical connections thereto · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10P72/7436 |
| Official title | {used to support a device or a wafer when forming electrical connections thereto} |
| Display label | used to support a device or a wafer when forming electrical connections thereto |
| Total patents | 2,552 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 84 |
| 2016 | 103 |
| 2017 | 117 |
| 2018 | 144 |
| 2019 | 227 |
| 2020 | 315 |
| 2021 | 347 |
| 2022 | 341 |
| 2023 | 320 |
| 2024 | 287 |
| 2025 | 236 |
| 2026 | 31 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor Package and Method of Manufacturing The Same
US-2024387196-A1 · Nov 21, 2024 · US
Advanced Structure for Info Wafer Warpage Reduction
US-2015380334-A1 · Dec 31, 2015 · US
Fan-Out Package Structure and Methods for Forming the Same
US-2015380388-A1 · Dec 31, 2015 · US
Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices
US-2015380340-A1 · Dec 31, 2015 · US
Method for producing a wafer provided with chips
US-9224630-B2 · Dec 29, 2015 · US
3D bond and assembly process for severely bowed interposer die
US-9224712-B2 · Dec 29, 2015 · US
Packaging process tools and packaging methods for semiconductor devices
US-9218999-B2 · Dec 22, 2015 · US
Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same
US-9214420-B2 · Dec 15, 2015 · US
Package-on-package with via on pad connections
US-9214450-B2 · Dec 15, 2015 · US
Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices
US-9209166-B2 · Dec 8, 2015 · US
Alignment mark design for packages
US-2015348904-A1 · Dec 3, 2015 · US
Ring structures in device die
US-2015348916-A1 · Dec 3, 2015 · US
Semiconductor device having a die and through substrate-via
US-9196587-B2 · Nov 24, 2015 · US
Electronic Device Package Including Metal Blocks
US-2015332938-A1 · Nov 19, 2015 · US
Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
US-9177848-B2 · Nov 3, 2015 · US
Semiconductor devices having conductive via structures and methods for fabricating the same
US-9171753-B2 · Oct 27, 2015 · US
Semiconductor device and manufacturing method for the same
US-2015303142-A1 · Oct 22, 2015 · US
Method of fabricating package structure
US-2015287691-A1 · Oct 8, 2015 · US
Prevention of warping during handling of chip-on-wafer
US-2015279812-A1 · Oct 1, 2015 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10P72/7436?
- CPC H10P72/7436 is the Cooperative Patent Classification code for “used to support a device or a wafer when forming electrical connections thereto.”
- How many patents are filed under CPC H10P72/7436 (used to support a device or a wafer when forming electrical connections thereto)?
- Our database includes 2,552 publications tagged with this CPC code.
- Is patent activity under CPC H10P72/7436 growing?
- Publication counts under this code: 287 in 2024 vs 236 in 2025 (latest complete years).