Wafer level die integration and method therefor

Patent metadata

Field	Value
Publication number	US-8975111-B2
Application number	US-201113170116-A
Country	US
Kind code	B2
Filing date	Jun 27, 2011
Priority date	Mar 4, 2008
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

A method of manufacturing a semiconductor device includes providing a wafer for supporting the semiconductor device. An insulation layer is disposed over a top surface of the wafer. The method includes forming a first interconnect structure over the top surface of the wafer with temperatures in excess of 200° C., forming a metal pillar over the wafer in electrical contact with the first interconnect structure, connecting a semiconductor component to the first interconnect structure, and forming encapsulant over the semiconductor component. The encapsulant is etched to expose a portion of the metal pillar. A buffer layer is optionally formed over the encapsulant. The method includes forming a second interconnect structure over the encapsulant in electrical contact with the metal pillar with temperatures below 200° C., and removing a portion of a backside of the wafer opposite the top surface of the wafer.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a first substrate;
forming an insulating layer over the first substrate;
forming a conductive layer over the insulating layer;
forming an interconnect structure over the conductive layer;
disposing a second substrate over the interconnect structure opposite the first substrate;
removing the first substrate;
forming an opening in the insulating layer over the conductive layer;
disposi…

Assignees

• Lin Yaojian
• Cao Haijing
• Stats Chippac Ltd

Inventors

• Lin Yaojian
• Cao Haijing

Classifications

• H10W74/00

  Electricity · mapped topic

• H10W70/63

  Electricity · mapped topic

• H10W72/884

  Electricity · mapped topic

• H10W90/754

  Electricity · mapped topic

• H10W72/877

  Electricity · mapped topic