Semiconductor devices and methods of manufacturing
US-12166025-B2 · Dec 10, 2024 · US
used as a support during manufacture of interconnect decals or build up layers
used as a support during manufacture of interconnect decals or build up layers · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10P72/743 |
| Official title | {used as a support during manufacture of interconnect decals or build up layers} |
| Display label | used as a support during manufacture of interconnect decals or build up layers |
| Total patents | 5,100 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 66 |
| 2016 | 132 |
| 2017 | 237 |
| 2018 | 299 |
| 2019 | 489 |
| 2020 | 606 |
| 2021 | 630 |
| 2022 | 615 |
| 2023 | 616 |
| 2024 | 720 |
| 2025 | 590 |
| 2026 | 100 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor package having multiple substrates
US-2024395683-A1 · Nov 28, 2024 · US
Method of manufacturing a semiconductor package having conductive pillars
US-2024387343-A1 · Nov 21, 2024 · US
Semiconductor Package and Method of Manufacturing The Same
US-2024387196-A1 · Nov 21, 2024 · US
High density vertical interconnect
US-2024332130-A1 · Oct 3, 2024 · US
Selective etching process for SiGe and doped epitaxial silicon
US-12062571-B2 · Aug 13, 2024 · US
Integrated fan-out package and manufacturing method thereof
US-2024178120-A1 · May 30, 2024 · US
Chuck, lamination process, and manufacturing method of semiconductor package using the same
US-11993066-B2 · May 28, 2024 · US
Semiconductor structure, stacked structure, and manufacturing method thereof
US-2024096849-A1 · Mar 21, 2024 · US
Integrated circuit package and method
US-11935804-B2 · Mar 19, 2024 · US
Workpiece chuck, workpiece handling apparatus, manufacturing method of semiconductor package
US-2024063048-A1 · Feb 22, 2024 · US
Semiconductor structure and manufacturing method thereof
US-2024063101-A1 · Feb 22, 2024 · US
Semiconductor package using a coreless signal distribution structure
US-11869879-B2 · Jan 9, 2024 · US
Back-end-of-line stack for a stacked device
US-2015371938-A1 · Dec 24, 2015 · US
Capping coating for 3D integration applications
US-9218956-B2 · Dec 22, 2015 · US
Recessed and embedded die coreless package
US-2015357312-A1 · Dec 10, 2015 · US
Package-on-package semiconductor device
US-2015357319-A1 · Dec 10, 2015 · US
Wire bond support structure and microelectronic package including wire bonds therefrom
US-2015348928-A1 · Dec 3, 2015 · US
Contact Pad for Semiconductor Device
US-2015348877-A1 · Dec 3, 2015 · US
Substrateless power device packages
US-2015340301-A1 · Nov 26, 2015 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10P72/743?
- CPC H10P72/743 is the Cooperative Patent Classification code for “used as a support during manufacture of interconnect decals or build up layers.”
- How many patents are filed under CPC H10P72/743 (used as a support during manufacture of interconnect decals or build up layers)?
- Our database includes 5,100 publications tagged with this CPC code.
- Is patent activity under CPC H10P72/743 growing?
- Publication counts under this code: 720 in 2024 vs 590 in 2025 (latest complete years).