Multi-stack package-on-package structures

Patent metadata

Field	Value
Publication number	US-10490540-B2
Application number	US-201715676202-A
Country	US
Kind code	B2
Filing date	Aug 14, 2017
Priority date	Nov 10, 2015
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die is coplanar with a bottom surface of the first encapsulating material. First dielectric layers are underlying the first device die. First redistribution lines are in the first dielectric layers and electrically coupling to the first device die. Second dielectric layers are overlying the first device die. Second redistribution lines are in the second dielectric layers and electrically coupling to the first redistribution lines. A second device die is overlying and electrically coupling to the second redistribution lines. No solder region connects the second device die to the second redistribution lines. A second encapsulating material encapsulates the second device die therein. A third device die is electrically coupled to the second redistribution lines. A third encapsulating material encapsulates the third device die therein.

First claim

What is claimed is:

1. A package comprising:
a first device die;
a first encapsulating material encapsulating the first device die therein;
first dielectric layers underlying the first device die, wherein both the first encapsulating material and the first device die are in contact with a top layer in the first dielectric layers;
first redistribution lines in the first dielectric layers and electrically coupling to the first device die;
second dielectric layers overlying the first device die;
second redistribution lines in the second dielectric layers and electrically coupling to the first redistribution lines;
a second device die overlying and electrically coupling to the second redistribution lines, wherein no solder region connects the second device die to the second redistribution lines, wherein the second device die comprises:
a semiconductor substrate; and
through-semiconductor vias penetrating through the semiconductor substrate;

a second encapsulating material encapsulating the second device die therein;
a third device die electrically coupling to the second redistribution lines, wherein the through-semiconductor vias electrically couple the second redistribution lines to the third device die; and
a third encapsulating material encapsulating the third device die therein.

2. The package of claim 1 , wherein the third device die is overlying the second device die, and no solder region is between the third device die and the first redistribution lines.

3. The package of claim 1 , wherein the third device die is overlying the second device die, and the package further comprises solder regions electrically coupling the third device die to the second redistribution lines.

4. The package of claim 1 further comprising a through-via penetrating through the second encapsulating material, wherein the through-via electrically couples the third device die to the second redistribution lines.

5. The package of claim 1 , wherein the through-semiconductor vias are electrically decoupled from all active and passive devices in the second device die.

6. The package of claim 5 , wherein no through-via penetrates through the second encapsulating material.

7. The package of claim 1 , wherein respective edges of the first dielectric layers, the second dielectric layers, the first encapsulating material, and the second encapsulating material are aligned with each other.

8. The package of claim 1 further comprising:
a die-attach film between and physically contacting the first device die and the second dielectric layers, wherein both the first device die and the second device die have front surfaces facing the first dielectric layers.

9. A package comprising:
a first plurality of dielectric layers, wherein the first plurality of dielectric layers has a bottom surface and a top surface;
a first through-via underlying and in contact with the bottom surface of the first plurality of dielectric layers;
a second through-via overlying and in contact with the top surface of the first plurality of dielectric layers;
a first device die and a second device die, wherein the second device die comprises:
a semiconductor substrate, and
a through-semiconductor via penetrating through the semiconductor substrate;

a first encapsulating material encapsulating the first device die and the first through-via therein; and
a second encapsulating material encapsulating the second device die and the second through-via therein, wherein the through-semiconductor via is electrically decoupled from all active and passive devices in the second device die.

10. The package of claim 9 , wherein a backside of the first device die and a front side of the second device die faces the first plurality of dielectric layers.

11. The package of claim 9 further comprising:
a second plurality of dielectric layers underlying and in contact with the first device die and the first through-via; and
a plurality of redistribution lines in the second plurality of dielectric layers, wherein the plurality of redistribution lines is electrically coupled to the first device die and the first through-via.

12. The package of claim 9 further comprising:
a third plurality of dielectric layers overlying and in contact with the second device die and the second encapsulating material;
an additional plurality of redistribution lines in the third plurality of dielectric layers, wherein the additional plurality of redistribution lines is electrically coupled to the second through-via;
a third device die over the third plurality of dielectric layers; and
a third encapsulating material encapsulating the third device die therein.

13. The package of claim 12 , wherein the third device die comprises a metal pillar, with the metal pillar in contact with both a conductive feature in the third plurality of dielectric layers and a top dielectric layer in the third plurality of dielectric layers.

14. A package comprising:
a first plurality of redistribution lines;
a first plurality of dielectric layers, with the first plurality of redistribution lines being in the first plurality of dielectric layers;
a first device die underlying the first plurality of dielectric layers;
an adhesive film in physical contact with both the first device die and one of the first plurality of dielectric layers;
a second device die comprising metal pads, wherein the metal pads are over and bonded to the first plurality of redistribution lines, wherein the second device die comprises:
a semiconductor substrate; and
a through-semiconductor via penetrating through the semiconductor substrate, wherein the through-semiconductor via is electrically decoupled from all active and passive devices in the second device die;

a first encapsulating material encapsulating the first device die therein, wherein the adhesive film is encapsulated in the first encapsulating material; and
a second encapsulating material encapsulating the second device die therein.

15. The package of claim 14 , wherein a top surface of the adhesive film and a top surface of the first encapsulating material are substantially coplanar.

16. The package of claim 14 , wherein a top surface of the adhesive film and a top surface of the first encapsulating material are in contact with a same dielectric layer in the first plurality of dielectric layers.

17. The package of claim 14 further comprising:
an additional dielectric layer over the second encapsulating material; and
an underfill overlying and in contact with the additional dielectric layer.

18. The package of claim 14 further comprising a second plurality of redistribution lines over the second device die, wherein the through-semiconductor via electrically couples the first plurality of redistribution lines to the second plurality of redistribution lines.

19. The package of claim 14 , wherein there is no solder region connecting the second device die to the first plurality of redistribution lines.

20. The package of claim 14 further comprising a through-via penetrating through the second encapsulating material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Su An-Jhih

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title