Method of forming semiconductor packages having through package vias

Patent metadata

Field	Value
Publication number	US-9899248-B2
Application number	US-201514723857-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	Dec 3, 2014
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer and protrude from the patterned layer to expose tapered sidewalls.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a first dielectric layer on a carrier substrate;
forming first openings in the first dielectric layer;
forming one or more seed layers along a top surface of the first dielectric layer, sidewalls of the first openings, and a bottom of the first openings;
forming through vias on the one or more seed layers, the through vias extending into the first openings;
placing a semiconductor die on a first surface of the first dielectric layer, the semiconductor die disposed between the through vias, the semiconductor die having die connectors facing away from the first surface of the first dielectric layer after the placing;
forming a molding compound adjacent sidewalls of the through vias and the semiconductor die;
planarizing the molding compound such that a top surface of the molding compound is planar with top surfaces of the through vias and top surfaces of the die connectors;
removing the carrier substrate after the planarizing the molding compound;
removing at least a portion of the one or more seed layers to expose a bottom portion of the through vias; and
removing a portion of the first dielectric layer, to expose a portion of sidewalls of the through vias.

2. The method of claim 1 , wherein the first openings have a positive taper.

3. The method of claim 1 , wherein the first openings have a negative taper.

4. The method of claim 1 , further comprising forming a redistribution structure on the semiconductor die and the through vias, the redistribution structure including dielectric layers and metallization patterns, the metallization patterns contacting the die connectors and the through vias.

5. The method of claim 1 , further comprising forming a sacrificial layer on the carrier substrate, and wherein the first dielectric layer is formed on the sacrificial layer.

6. The method of claim 5 , further comprising removing the sacrificial layer before the removing the at least a portion of the one or more seed layers.

7. A method of manufacturing a semiconductor device, the method comprising:
forming a first dielectric layer over a substrate;
forming one or more seed layers over the first dielectric layer;
forming through vias over the one or more seed layers, the one or more seed layers and the through vias extending through the first dielectric layer;
placing an integrated circuit die over the first dielectric layer, the integrated circuit die disposed between the through vias after the placing;
forming an encapsulant between the integrated circuit die and the through vias;
planarizing the encapsulant such that a top surface of the encapsulant is planar with top surfaces of the through vias and a top surface of the integrated circuit die;
removing the substrate after the planarizing the encapsulant; and
removing a portion of the one or more seed layers and a portion of the first dielectric layer to expose a portion of sidewalls of the through vias.

8. The method of claim 7 , further comprising forming a redistribution structure over the through vias and the integrated circuit die, the redistribution structure including dielectric layers and metallization patterns, the metallization patterns electrically coupled to the through vias and the integrated circuit die.

9. The method of claim 7 , wherein the through vias comprise a first body portion extending through the encapsulant having a first width and a second body portion extending through the first dielectric layer having a second width different than the first width.

10. The method of claim 9 , wherein the second width is less than the first width.

11. The method of claim 9 , wherein the second body portion is tapered.

12. The method of claim 7 , further comprising forming a sacrificial layer before forming the first dielectric layer.

13. A method of manufacturing a semiconductor device, the method comprising:
forming a first dielectric layer over a substrate;
forming one or more seed layers over the first dielectric layer;
forming through vias over the one or more seed layers, the one or more seed layers and the through vias extending through the first dielectric layer;
placing an integrated circuit die over a first side of the first dielectric layer, the integrated circuit die disposed between the through vias, the integrated circuit die having die connectors facing away from the first side of the first dielectric layer after the placing;
forming an encapsulant between the integrated circuit die and the through vias;
planarizing the encapsulant such that a top surface of the encapsulant is planar with top surfaces of the through vias and top surfaces of the die connectors;
removing the substrate after the planarizing the encapsulant; and
removing a portion of the one or more seed layers and a portion of the first dielectric layer to expose a portion of sidewalls of the through vias, the portion of the sidewalls of the through vias being on protrusions of the through vias, the protrusions extending through a second side of the first dielectric layer.

14. The method of claim 13 , further comprising thinning the first dielectric layer.

15. The method of claim 13 , further comprising forming a redistribution structure on the integrated circuit die and each of the through vias, the redistribution structure including dielectric layers and metallization patterns, the metallization patterns electrically coupled to the integrated circuit die and each of the through vias.

16. The method of claim 13 , wherein the forming the plurality of through vias comprises:
forming first openings in the first dielectric layer;
growing the one or more seed layers along a top surface of the first dielectric layer, sidewalls of the first openings, and bottom of the first openings;
forming a patterning layer over the portions of the seed layers along the top surface of the first dielectric layer;
forming a conductive material over the portions of the seed layers not covered by the patterning layer; and
removing the patterning layer.

17. The method of claim 13 , wherein the through vias surround the integrated circuit die.

18. The method of claim 13 , wherein the protrusions of the through vias protrude a distance of 1 μm to 5 μm from the first dielectric layer.

19. The method of claim 13 , wherein:
the integrated circuit die is disposed between the through vias after the placing; and
the planarizing the encapsulant comprises planarizing the encapsulant such that the top surface of the encapsulant is planar with the top surfaces of the through vias and a top surface of the integrated circuit die.

20. The method of claim 13 , wherein the through vias comprise a first body portion extending through the encapsulant having a first width and a second body portion extending through the first dielectric layer having a second width different than the first width.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen Hua
• Liu Chung Shi
• Lin Chih Wei
• Kuo Hung Jui
• Cheng Ming Da
• Hu Yu Hsiang

Classifications

• H10P72/7448

  the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/073

  of die-attach connectors · CPC title