Bump structure and method of making the same

Patent metadata

Field	Value
Publication number	US-11417539-B2
Application number	US-202017085346-A
Country	US
Kind code	B2
Filing date	Oct 30, 2020
Priority date	Feb 27, 2020
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming one or more first conductive layers over a substrate;
forming a first photoresist layer over the one or more first conductive layers;
etching the one or more first conductive layers by using the first photoresist layer as an etching mask, to form an island pattern of the one or more first conductive layers separated from a bus bar pattern of the one or more first conductive layers by a ring shaped groove;
forming a connection pattern to connect the island pattern and the bus bar pattern;
forming a second photoresist layer over the one or more first conductive layers and the connection pattern, the second photoresist layer including an opening over the island pattern;
forming one or more second conductive layers on the island pattern in the opening;
removing the second photoresist layer; and
removing the connection pattern, thereby forming a bump structure.

2. The method of claim 1 , wherein the connection pattern is made of a conductive material different from the one or more first conductive layers and the one or more second conductive layers.

3. The method of claim 1 , wherein the connection pattern only partially fills the ring shape groove to connect the island pattern and the bus bar pattern.

4. The method of claim 3 , wherein the connection pattern is formed in a part of the ring shape groove and on a part of an upper surface of an uppermost layer of the one or more first conductive layers.

5. The method of claim 3 , wherein a part of the connection pattern is disposed in the opening.

6. The method of claim 1 , wherein the connection pattern is removed by wet etching.

7. The method of claim 1 , wherein after the connection pattern is removed, the bump structure includes an under-cut between the bump structure and an uppermost layer of the one or more first conductive layers.

8. The method of claim 7 , wherein the under-cut is only partially formed and no under-cut is formed at a remaining part between the bump structure and the uppermost layer of the one or more first conductive layers.

9. A method of fabricating a semiconductor device, comprising:
forming a pad electrode coupled to a semiconductor circuit formed over a substrate;
forming a passivation layer over the pad electrode;
patterning the passivation layer to expose at least a part of the pad electrode;
forming a seed layer over the passivation layer and the pad electrode;
patterning the seed layer to form an island pattern of the seed layer electrically separated from a bus bar pattern of the seed layer by a ring shape groove;
forming a connection pattern to electrically connect the island pattern and the bus bar pattern;
forming a photoresist layer over the seed layer and the connection pattern, the photoresist layer including an opening over the island pattern;
forming one or more conductive layers on the island pattern in the opening;
removing the photoresist layer; and
removing the connection pattern, thereby forming a bump structure.

10. The method of claim 9 , wherein at least one of the one or more conductive layers is formed by an electroplating process.

11. The method of claim 10 , wherein the bus bar pattern is electrically connected to a potential in the electroplating process.

12. The method of claim 10 , wherein the seed layer includes copper or a copper alloy.

13. The method of claim 10 , wherein the at least one of the one or more conductive layers includes copper or a copper alloy.

14. The method of claim 9 , further comprising forming an underlying conductive layer over the passivation layer and the pad electrode, before forming the seed layer.

15. The method of claim 14 , wherein the underlying conductive layer includes at least one selected from the group consisting of a titanium-based metal, a gold-based metal, and a copper-based metal.

16. The method of claim 9 , wherein the connection pattern includes at least one selected from the group consisting of Al, Au, Cr, Fe, Mn, Mg, Mo, Ni, Nb, Ta, Ti, W, Zn, and alloys thereof.

17. A method of fabricating a semiconductor device, comprising:
forming a plurality of pad electrodes each coupled to a semiconductor circuit formed over a substrate;
forming a passivation layer over the plurality of pad electrodes;
patterning the passivation layer to expose at least a part of each of the plurality of pad electrodes;
forming a first conductive layer over the passivation layer and the plurality of pad electrodes;
forming a seed layer over the first conductive layer;
patterning the seed layer and the first conductive layer to form a plurality of island patterns of the seed layer and the first conductive layer electrically separated from each other, a bus bar pattern of the seed layer, and the first conductive layer by a plurality of ring shaped grooves surrounding a corresponding one of the plurality of island patterns;
forming a plurality of connection patterns to electrically connect the plurality of island patterns and the bus bar pattern, respectively;
forming a photoresist layer over the seed layer and the plurality of connection patterns, the photoresist layer including a plurality of openings over the plurality of island patterns;
forming one or more second conductive layers on the plurality of island patterns in the plurality of openings;
removing the photoresist layer; and
removing the plurality of connection patterns, thereby forming a plurality of bump structures over the plurality of pad electrodes.

18. The method of claim 17 , wherein at least one of the one or more second conductive layers is formed by an electroplating process.

19. The method of claim 17 , wherein the plurality of connection patterns are made of a conductive material different from the seed layer, the first conductive layer and the one or more second conductive layers.

20. The method of claim 17 , wherein:
a part of each of the plurality of connection patterns is disposed in a corresponding one of the plurality of openings, and
a lowermost layer of the one or more second conductive layers is in contact with the part of each of the plurality of connection patterns.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Wen-Hsiung
• Cheng Ming-Da
• Lin Su-Fei
• Liu Hsu-Lun
• Chan Chien-Pin
• Lin Yung-Sheng

Classifications

• H10W90/701 Primary

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/095

  of vias therein · CPC title