Package with UBM and methods of forming

Patent metadata

Field	Value
Publication number	US-10147692-B2
Application number	US-201514671477-A
Country	US
Kind code	B2
Filing date	Mar 27, 2015
Priority date	Sep 15, 2014
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.

First claim

What is claimed is:

1. A package comprising:
an integrated circuit die;
an encapsulant at least laterally encapsulating the integrated circuit die;
a redistribution structure on the integrated circuit die and the encapsulant, the redistribution structure comprising a first dielectric layer;
a second dielectric layer over the redistribution structure, the second dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die, the redistribution structure being disposed between the integrated circuit die and the second dielectric layer;
a connector support metallization coupled to the redistribution structure, the connector support metallization having a first portion on the first surface of the second dielectric layer and having a second portion extending in an opening through the second dielectric layer;
a dummy pattern on the first surface of the second dielectric layer and around the connector support metallization, the dummy pattern being laterally spaced apart from the connector support metallization and being electrically isolated, the dummy pattern having a first sidewall facing the connector support metallization and having a second sidewall facing away from the connector support metallization, a first surface of the dummy pattern distal the second dielectric layer having a perimeter portion and a center portion, the perimeter portion being further from the connector support metallization than the center portion;
a third dielectric layer on the first surface of the second dielectric layer, the third dielectric layer being laterally spaced part from the connector support metallization, the third dielectric layer covering the second sidewall of the dummy pattern and exposing the first sidewall of the dummy pattern, the third dielectric layer covering the perimeter portion of the first surface of the dummy pattern and exposing the center portion of the first surface of the dummy pattern; and
an external connector on the connector support metallization.

2. The package of claim 1 , wherein the dummy pattern surrounds and defines an area of the first surface of the second dielectric layer, the connector support metallization being in the area of the first surface of the second dielectric layer, the third dielectric layer not contacting the area of the first surface of the second dielectric layer.

3. The package of claim 1 , wherein the dummy pattern has a width parallel to the first surface of the second dielectric layer, the third dielectric layer being on at least half of the width of the dummy pattern laterally distal from the connector support metallization.

4. The package of claim 1 , wherein the dummy pattern has a width parallel to the first surface of the second dielectric layer, the third dielectric layer being on half of the width of the dummy pattern laterally distal from the connector support metallization, the third dielectric layer not being on half of the width of the dummy pattern laterally proximate to the connector support metallization.

5. The package of claim 1 , wherein the dummy pattern has a width parallel to the first surface of the second dielectric layer, the width being in a range from 5 μm to 10 μm.

6. The package of claim 1 , wherein the dummy pattern is laterally separated from the connector support metallization by at least 40 μm.

7. The package of claim 1 further comprising an adhesion layer on at least a portion of the dummy pattern.

8. The package of claim 7 , wherein the adhesion layer comprises an oxide.

9. A package comprising:
an integrated circuit die;
an encapsulant at least laterally encapsulating the integrated circuit die;
a redistribution structure over the integrated circuit die and the encapsulant, the redistribution structure comprising a metallization pattern and a first dielectric layer;
a second dielectric layer over the redistribution structure, wherein a first opening is defined though the second dielectric layer, and wherein the metallization pattern defines at least a portion of a bottom surface of the first opening;
a connector support metallization coupled to the redistribution structure, the connector support metallization having a first portion over a first surface of the second dielectric layer distal the redistribution structure, a second portion extending along the bottom surface of the first opening through the second dielectric layer, and a third portion extending along a sidewall of the first opening and between the first portion and the second portion, an upper surface of the second portion being closer to the integrated circuit die than an upper surface of the first portion, a joint being formed at a location where the second portion meets the third portion;
a third dielectric layer over the first surface of the second dielectric layer, the third dielectric layer contacting the first portion, the third portion, and at least a portion of the second portion of the connector support metallization; and
an external connector through a second opening through the third dielectric layer and on the connector support metallization.

10. The package of claim 9 , wherein the third dielectric layer is on the first portion of the connector support metallization and extends from the joint toward a center of the first portion of the connector support metallization by at least a distance of 10 μm.

11. The package of claim 9 further comprising an adhesion layer on at least the first portion of the connector support metallization.

12. The package of claim 9 , wherein the second portion of the connector support metallization contacts the metallization pattern of the redistribution structure.

13. The package of claim 9 , wherein the external connector comprises solder.

14. A package structure comprising:
an encapsulant at least laterally surrounding an integrated circuit die;
a first isolation layer over the integrated circuit die and the encapsulant, the first isolation layer having a first surface distal from the integrated circuit die and the encapsulant;
an under ball metallization (UBM) and a dummy pattern on the first surface of the first isolation layer, the dummy pattern comprising a continuous ring structure surrounding the UBM on the first surface of the first isolation layer, the dummy pattern being electrically isolated;
a second isolation layer on the first surface of the first isolation layer and contacting at least a portion of a first surface of the dummy pattern distal the first isolation layer, wherein the second isolation layer is laterally separated from the UBM, wherein the second isolation layer covers outer sidewalls of the dummy pattern facing away from UBM and covers a perimeter portion of the first surface of the dummy pattern, and wherein the second isolation layer exposes inner sidewalls of the dummy pattern facing the UBM and exposes a center portion of the first surface of the dummy pattern; and
an external electrical connector on the UBM.

15. The package structure of claim 14 further comprising an adhesion layer on at least a portion of the first surface of the dummy pattern.

16. The package structure of claim 14 , wherein the dummy pattern has a width parallel to the first surface of the first isolation layer, the second isolation layer being on at least half of the width of the dummy pattern laterally distal from the UBM.

17. The package structure of claim 14 , wherein the dummy pattern is physically separated from the UBM.

18. The package structure of claim 14 , wherein the UBM contacts a metallization pattern of a red

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hsien-Wei
• Huang Li-Hsien

Classifications

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/01955

  by using masks · CPC title