Enhancement of yield of functional microelectronic devices

Patent metadata

Field	Value
Publication number	US-11346882-B2
Application number	US-201816179492-A
Country	US
Kind code	B2
Filing date	Nov 2, 2018
Priority date	Nov 3, 2017
Publication date	May 31, 2022
Grant date	May 31, 2022

Abstract

Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

First claim

What is claimed is:

1. A method of facilitating yield of functional microelectronic devices in coordination with semiconductor fabrication, the method comprising:
gathering fabrication metrology data of a semiconductor wafer, wherein the fabrication metrology data includes measurements of one or more characteristics of the semiconductor wafer formed during semiconductor fabrication, each measurement being associated with spatial location of the semiconductor wafer where such measurement is made;
detecting non-conformities of the semiconductor wafer by comparing the gathered fabrication metrology data to at least one metrology data threshold;
identifying a non-conforming region of the semiconductor wafer comprising an aggregation of the detected non-conformities falling within a predetermined measure of adjacentness, the non-conforming region being a subregion of the semiconductor wafer;
determining a systemic impact of the non-conformities in the non-conforming region on projected electrical-mechanical functionality of microelectronic devices formed at least in part by the non-conforming region; and
altering the semiconductor fabrication to decrease the systemic impact of the non-conformities in the non-conforming region.

2. The method of claim 1 , wherein altering the semiconductor fabrication to decrease the systemic impact of the non-conformities in the non-conforming region comprises:
choosing at least one semiconductor fabrication tool;
selecting at least one change in operation of the at least one chosen semiconductor fabrication tool;
simulating a semiconductor wafer fabrication in accordance with the at least one selected change in the operation of the at least one chosen semiconductor fabrication tool; and
estimating an effect of electrical-mechanical properties or functionality of microelectronic devices formed by the simulated semiconductor wafer fabrication.

3. The method of claim 2 , wherein the at least one semiconductor fabrication tool comprises a photolithography tool.

4. The method of claim 2 , wherein the at least one semiconductor fabrication tool is selected from a group consisting of a deposition tool, a track tool, an etch tool, and a cleaning tool.

5. The method of claim 1 , wherein altering the semiconductor fabrication to decrease the systemic impact of the non-conformities in the non-conforming region comprises:
choosing a combination of multiple semiconductor fabrication tools;
selecting at least one change in operation of each of the chosen combination of semiconductor fabrication tools;
simulating a semiconductor wafer fabrication in accordance with the at least one selected change in the operation of each of the chosen combination of semiconductor fabrication tools; and
estimating an effect of electrical-mechanical properties or functionality of microelectronic devices formed by the simulated semiconductor wafer fabrication.

6. The method of claim 1 , wherein altering the semiconductor fabrication to decrease the systemic impact of the non-conformities in the non-conforming region comprises at least one change in operation of at least one semiconductor fabrication tool.

7. A method of facilitating yield of functional microelectronic devices in coordination with semiconductor fabrication, the method comprising:
gathering fabrication metrology data of a semiconductor wafer, wherein the fabrication metrology data includes measurements of one or more characteristics of the semiconductor wafer formed during semiconductor fabrication, each measurement being associated with a spatial location of the semiconductor wafer where such measurement is made;
detecting non-conformities of the semiconductor wafer by comparing the gathered fabrication metrology data to at least one metrology data threshold;
identifying a non-conforming region of the semiconductor wafer comprising an aggregation of the detected non-conformities falling within a predetermined measure of adjacentness, the non-conforming region being a subregion of the semiconductor wafer; and
determining a systemic impact of the non-conformities in the non-conforming region on projected electrical-mechanical functionality of microelectronic devices formed at least in pail by the non-conforming region.

8. The method of claim 7 , further comprising:
choosing at least one semiconductor fabrication tool;
selecting at least one change in operation of the at least one chosen semiconductor fabrication tool, wherein the at least one change alters the semiconductor fabrication, and wherein the at least one semiconductor fabrication tool is selected from a group consisting of a deposition tool, a track tool, an etch tool, and a cleaning tool;
simulating a semiconductor wafer fabrication in accordance with the at least one selected change in operation of the at least one chosen semiconductor fabrication tool; and
estimating an effect of electrical-mechanical properties or functionality of the microelectronic devices formed by the simulated semiconductor wafer fabrication.

9. A non-transitory computer-readable storage medium storing instructions to be executed by one or more processors in coordination with semiconductor fabrication of a semiconductor wafer, wherein the instructions cause the one or more processors to:
gather fabrication metrology data of the semiconductor wafer, wherein the fabrication metrology data includes measurements of one or more characteristics of the semiconductor wafer formed in the semiconductor fabrication, each measurement being associated with a spatial location of the semiconductor wafer where such measurement is made;
detect non-conformities of the semiconductor wafer by comparing the gathered fabrication metrology data to at least one metrology data threshold;
identify a non-conforming region of the semiconductor wafer comprising an aggregation of the detected non-conformities falling within a predetermined measure of adjacentness, the non-conforming region being a subregion of the semiconductor wafer;
determine a systemic impact of the non-conformities in the non-conforming region on projected electrical-mechanical functionality of microelectronic devices formed at least in part by the non-conforming region; and
alter the semiconductor fabrication to decrease the systemic impact of ameliorate the non-conformities in the non-conforming region.

10. The non-transitory computer-readable storage medium of claim 9 wherein the instructions to alter the semiconductor fabrication to decrease the systemic impact of the non-conformities in the non-conforming region cause the one or more processors to
choose at least one semiconductor fabrication tool;
select at least one change in operation of the at least one chosen semiconductor fabrication tool;
simulate a semiconductor wafer fabrication in accordance with the at least one selected change in operation of the at least one chosen semiconductor fabrication tool; and
estimate an effect of electrical-mechanical properties or functionality of microelectronic devices formed by the simulated semiconductor wafer fabrication.

11. The non-transitory computer-readable storage medium of claim 10 , wherein the at least one semiconductor fabrication tool comprises a photolithography tool.

12. The non-transitory computer-readable storage medium of claim 10 , wherein the at least one semiconductor fabrication tool is selected from a group consisting of a deposition tool, a track tool, an etch tool, and a cleaning tool.

13. The non-transitory computer-readable storage medium of claim 9 , wherein the instructions to alter the semiconductor fabrication to decrease the systemic impact of the non-confor

Assignees

• Tokyo Electron Ltd

Inventors

• Fonseca Carlos A
• Ip Nathan
• Estrella Joel

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P72/0612

  Production flow monitoring, e.g. for increasing throughput · CPC title

• G01R31/2831 Primary

  Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00) · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title