Enhancement of yield of functional microelectronic devices

Patent metadata

Field	Value
Publication number	US-2019137565-A1
Application number	US-201816179526-A
Country	US
Kind code	A1
Filing date	Nov 2, 2018
Priority date	Nov 3, 2017
Publication date	May 9, 2019
Grant date	—

Abstract

Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

First claim

What is claimed is:

1 . A method that facilitates yield of functional microelectronic devices in coordination with semiconductor fabrication, wherein semiconductor fabrication includes forming a collection of microelectronic devices from layers of a semiconductor wafer, the method comprising:
gathering fabrication metrology data of the semiconductor wafer, wherein the fabrication metrology data includes measurements of one or more characteristics of the wafer formed in the semiconductor fabrication and each measurement being associated with a spatial location of the wafer from where such measurement is made; generating a model of the semiconductor wafer based on the gathered fabrication metrology data of the semiconductor wafer; based on the generated model, detecting non-conformities of the semiconductor wafer based on the gathered fabrication metrology data; identifying a non-conforming region of the semiconductor wafer, wherein the non-conforming region includes an aggregation of neighboring non-conformities; determining the systemic impact on the non-conformities in the non-conforming regions on the functionality of the microelectronic devices formed at least in part in the non-conforming region.

2 . The method of claim 1 , wherein the gathering of fabrication metrology data includes:
measurements from multiple semiconductor wafers using a common stack of patterns of materials as the layers of the semiconductors being fabricated; measuring and/or calculating fabrication metrology data selected from a group consisting of edge placement error (EPE); grid critical dimension (CD) measurements; block line width roughness (LWR) measurements; grid LWR measurements; block CD measurements; profile; cross-section; selective deposition; electrical properties of the formed microelectronic devices; contact hole CD; contact hole roughness; CER and ellipticity; short trenches tip-to-tip distance; line tip-to-tip distance; layer-to-layer displacement data; overlay data; film thicknesses and uniformities; measurements that occur after actions of a single tool; measurements that occur after all of the tools of a single layer; measurements that occur after multiple layers; and a combination thereof.

3 . The method of claim 1 , wherein a non-conformity is an area of an active layer with characteristics that are capable of being measured and/or where such measurements fall outside a defined range and/or threshold.

4 . The method of claim 1 further comprising forming a visualization of the gathered fabrication metrology data of the semiconductor wafer.

5 . The method of claim 4 , wherein the formation of the visualization includes producing an image of the wafer with particular colors and/or shading that corresponds to particular locations of the wafer are associated with measured and/or calculated range of fabrication metrology data.

6 . The method of claim 4 , wherein the formation of the visualization includes producing an image of the wafer with particular colors and/or shading that corresponds to particular locations of the wafer are associated with the non-conforming region.

7 . A non-transitory computer-readable storage medium comprising instructions that when executed cause a processor of a computing device to perform operations in coordination with semiconductor fabrication by forming a collection of microelectronic devices from layers of a semiconductor wafer, the operations comprising:
gathering fabrication metrology data of the semiconductor wafer, wherein the fabrication metrology data includes measurements of one or more characteristics of the wafer formed in the semiconductor fabrication and each measurement being associated with a spatial location of the wafer from where such measurement is made; generating a model of the semiconductor wafer based on the gathered fabrication metrology data of the semiconductor wafer; based on the generated model, detecting non-conformities of the semiconductor wafer based on the gathered fabrication metrology data; identifying a non-conforming region of the semiconductor wafer, wherein the non-conforming region includes an aggregation of neighboring non-conformities; determining the systemic impact on the non-conformities in the non-conforming regions on the functionality of the microelectronic devices formed at least in part by the non-conforming region.

8 . The non-transitory computer-readable storage medium of claim 7 further comprising forming a visualization of the gathered fabrication metrology data of the semiconductor wafer.

9 . The non-transitory computer-readable storage medium of claim 8 , wherein the formation operation includes producing an image of the wafer with particular colors and/or shading that corresponds to particular locations of the wafer are associated with measured and/or calculated the range of fabrication metrology data.

10 . A non-transitory computer-readable storage medium of claim 8 , wherein the formation operation includes producing an image of the wafer with particular colors and/or shading that corresponds to particular locations of the wafer are associated with the non-conforming region.

11 . A method comprising:
gathering fabrication metrology data of the semiconductor wafer, wherein the fabrication metrology data includes measurements of one or more characteristics of the wafer formed in the semiconductor fabrication and each measurement being associated with a spatial location of the wafer from where such measurement is made; generating a model of the semiconductor wafer based on the gathered fabrication metrology data of the semiconductor wafer; based on the generated model, detecting non-conformities of the semiconductor wafer based on the gathered fabrication metrology data; identifying a non-conforming region of the semiconductor wafer, wherein the non-conforming region includes an aggregation of neighboring non-conformities; determining the systemic impact on the non-conformities in the non-conforming regions on the functionality of the microelectronic devices formed at least in part by the non-conforming region.

12 . The method of claim 11 further comprising forming a fingerprint, which is a visualization of the gathered fabrication metrology data of the semiconductor wafer.

13 . The method of claim 12 , wherein the formation of the fingerprint includes producing an image of the wafer with particular colors and/or shading that corresponds to particular locations of the wafer are associated with measured and/or calculated range of fabrication metrology data.

Assignees

• Tokyo Electron Ltd

Inventors

• Fonseca Carlos A
• Ip Nathan
• Estrella Joel

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P72/0612

  Production flow monitoring, e.g. for increasing throughput · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/30

  Circuit design · CPC title