Enhancement of yield of functional microelectronic devices

Patent metadata

Field	Value
Publication number	US-2019139798-A1
Application number	US-201816179492-A
Country	US
Kind code	A1
Filing date	Nov 2, 2018
Priority date	Nov 3, 2017
Publication date	May 9, 2019
Grant date	—

Abstract

Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

First claim

What is claimed is:

1 . A method that facilitates yield of functional microelectronic devices in coordination with semiconductor fabrication, wherein semiconductor fabrication includes forming a collection of microelectronic devices from layers of a semiconductor wafer, the method comprising:
gathering fabrication metrology data of the semiconductor wafer, wherein the fabrication metrology data includes measurements of one or more characteristics of the wafer formed in the semiconductor fabrication and each measurement being associated with a spatial location of the wafer from where such measurement is made; detecting non-conformities of the semiconductor wafer based on the gathered fabrication metrology data; identifying a non-conforming region of the semiconductor wafer, wherein the non-conforming region includes an aggregation of neighboring non-conformities; determining the systemic impact on the non-conformities in the non-conforming regions on the functionality of the microelectronic devices formed at least in part by the non-conforming region; ameliorating the non-conformities in the non-conforming regions that are determined to have a systemic impact on the electrical-mechanical functionality of the microelectronic device being formed as part of the semiconductor wafer.

2 . The method of claim 1 , wherein the amelioration includes:
choosing at least one semiconductor fabrication tool; selecting at least one change in the operation of the chosen semiconductor fabrication tool, where the at least one change alters the semiconductor fabrication; simulating a fabrication of a semiconductor wafer in accordance with the selected change in the operation of the chosen semiconductor fabrication tool; estimating the effect of the electrical-mechanical properties and/or functionality of the microelectronic devices formed by the simulated semiconductor wafer.

3 . The method of claim 1 , wherein the amelioration includes:
choosing a combination of multiple semiconductor fabrication tools; selecting at least one change in the operation of each of the chosen semiconductor fabrication tools, wherein the changes alter the semiconductor fabrication; simulating a fabrication of a semiconductor wafer in accordance with the selected change in the operation of each of the chosen semiconductor fabrication tools; estimating the effect of the electrical-mechanical properties and/or functionality of the microelectronic devices formed by the simulated semiconductor wafer.

4 . The method of claim 1 , wherein the amelioration includes at least one change in the operation of at least one semiconductor fabrication tool, wherein the at least one change alters the semiconductor fabrication.

5 . The method of claim 1 , wherein the amelioration includes at least one change in the operation of at least one of the chosen semiconductor fabrication tools, wherein the changes alter the semiconductor fabrication.

6 . The method of claim 1 , wherein the tool or tools of semiconductor fabrication is selected from a group comprising a deposition tool, a track tool, a photolithography tool, an etch tool, and a cleaning tool.

7 . A non-transitory computer-readable storage medium comprising instructions that when executed cause a processor of a computing device to perform operations in coordination with semiconductor fabrication by forming a collection of microelectronic devices from layers (e.g., a stack of patterns of materials) of a semiconductor wafer, the operations comprising:
gathering fabrication metrology data of the semiconductor wafer, wherein the fabrication metrology data includes measurements of one or more characteristics of the wafer formed in the semiconductor fabrication and each measurement being associated with a spatial location of the wafer from where such measurement is made; detecting non-conformities of the semiconductor wafer based on the gathered fabrication metrology data; identifying a non-conforming region of the semiconductor wafer, wherein the non-conforming region includes an aggregation of neighboring non-conformities; determining the systemic impact on the non-conformities in the non-conforming regions on the functionality of the microelectronic devices formed at least in part by the non-conforming region; ameliorating the non-conformities in the non-conforming regions that are determined to have a sufficient systemic impact on the electrical-mechanical functionality of the microelectronic device being formed as part of the semiconductor wafer.

8 . The non-transitory computer-readable storage medium of claim 7 , wherein the amelioration operation includes:
choosing at least one semiconductor fabrication tool; selecting at least one change in the operation of the chosen semiconductor fabrication tool, where the at least one change alters the semiconductor fabrication; simulating a fabrication of a semiconductor wafer in accordance with the selected change in the operation of the chosen semiconductor fabrication tool; estimating the effect of the electrical-mechanical properties and/or functionality of the microelectronic devices formed by the simulated semiconductor wafer.

9 . The non-transitory computer-readable storage medium of claim 7 , wherein the amelioration operation includes:
choosing a combination of multiple semiconductor fabrication tools; selecting at least one change in the operation of at least one of the chosen semiconductor fabrication tools, wherein the changes alter the semiconductor fabrication; simulating a fabrication of a semiconductor wafer in accordance with the selected change in the operation of each of the chosen semiconductor fabrication tools; estimating the effect of the electrical-mechanical properties and/or functionality of the microelectronic devices formed by the simulated semiconductor wafer.

10 . The non-transitory computer-readable storage medium of claim 7 , wherein the amelioration operation includes at least one change in the operation of at least one semiconductor fabrication tool, wherein the at least one change alters the semiconductor fabrication.

11 . The non-transitory computer-readable storage medium of claim 7 , wherein the amelioration operation includes at least one change in the operation of each of the chosen semiconductor fabrication tools, wherein the changes alter the semiconductor fabrication.

12 . The non-transitory computer-readable storage medium of claim 7 , wherein the amelioration operation includes at least one change in the operation of each of the chosen semiconductor fabrication tools, wherein the changes alter the semiconductor fabrication.

13 . The non-transitory computer-readable storage medium of claim 7 , wherein the tool or tools of semiconductor fabrication is selected from a group consisting of a deposition tool, a track tool, a photolithography tool, an etch tool, and a cleaning tool.

14 . A method that facilitates yield of functional microelectronic devices in coordination with semiconductor fabrication, wherein semiconductor fabrication includes forming a collection of microelectronic devices from layers of a semiconductor wafer, the method comprising:
gathering fabrication metrology data of the semiconductor wafer, wherein the fabrication metrology data includes measurements of one or more characteristics of the wafer formed in the semiconductor fabrication and each measurement being associated with a spatial location of the wafer from where such measurement is made; detecting non-conformities of the semiconductor wafer based on the gathered fabrication metrology data; identifying a non-conforming region o

Assignees

• Tokyo Electron Ltd

Inventors

• Fonseca Carlos A
• Ip Nathan
• Estrella Joel

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P72/0612

  Production flow monitoring, e.g. for increasing throughput · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/30

  Circuit design · CPC title