Three-dimensional semiconductor memory devices having source structure overlaps buried insulating layer

Patent metadata

Field	Value
Publication number	US-11114461-B2
Application number	US-201916700059-A
Country	US
Kind code	B2
Filing date	Dec 2, 2019
Priority date	Apr 30, 2019
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor lavers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device, comprising:
first and second semiconductor layers horizontally spaced apart from each other;
a buried insulating layer between the first and second semiconductor layers;
a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and
an isolation structure disposed on the buried insulating layer between the first and second cell array structures,
wherein the first cell array structure comprises:
an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and
a first source structure disposed between the first semiconductor layer and the electrode structure,

the first source structure is extended onto the buried insulating layer, and
the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.

2. The 3D semiconductor memory device of claim 1 , wherein the first and second source structures of the first and second cell array structures are electrically separated from each other by the isolation structure.

3. The 3D semiconductor memory device of claim 1 , wherein the first source structure of the first cell array structure is in contact with a side surface of the isolation structure.

4. The 3D semiconductor memory device of claim 1 , wherein a bottom surface of the isolation structure is in contact with the buried insulating layer.

5. The 3D semiconductor memory device of claim 1 , wherein the first cell array structure comprises an electrode isolation structure penetrating the electrode structure and the first source structure,
the electrode isolation structure has a line shape extending in a direction parallel to the top surface of the first semiconductor layer, and
the isolation structure comprises a same material as the electrode isolation structure.

6. The 3D semiconductor memory device of claim 5 , wherein a top surface of the isolation structure is at a same height as a top surface of the electrode isolation structure.

7. The 3D semiconductor memory device of claim 5 , wherein the first cell array structure comprises vertical structures penetrating the electrode structure and the first source structure, and
each of the vertical structures is extended into the first semiconductor layer.

8. The 3D semiconductor memory device of claim 7 , wherein the vertical structures are connected to the first source structure.

9. The 3D semiconductor memory device of claim 7 , Wherein the first cell array structure comprises bit lines, which are disposed on the electrode structure and are connected to the vertical structures, and
a top surface of the isolation structure is higher than top surfaces of the vertical structures and lower than bottom surfaces of the bit lines.

10. The 3D semiconductor memory device of claim 1 , wherein the first cell array structure comprises:
vertical structures penetrating the electrode structure and the first source structure; and
bit lines disposed on the electrode structure and connected to the vertical structures;
wherein a top surface of the isolation structure is higher than top surfaces of the vertical structures and lower than bottom surfaces of the bit lines.

11. The 3D semiconductor memory device of claim 1 , further comprising a peripheral circuit structure on a substrate,
wherein the peripheral circuit structure comprises peripheral circuits, which are disposed on the substrate, and a lower insulating layer, which covers the peripheral circuits, and
the first and second semiconductor layers and the buried insulating layer are disposed on the lower insulating layer.

12. The 3D semiconductor memory device of claim 1 , wherein the isolation structure comprises a conductive pattern and an insulating spacer between the first and second source structures and the conductive pattern.

13. The 3D semiconductor memory device of claim 1 , further comprising an insulating layer disposed on the buried insulating layer and filling a region between the first and second cell array structures,
wherein the isolation structure is extended in the direction perpendicular to the top surface of the first semiconductor layer, and penetrates at least a portion of the insulating layer.

14. A three-dimensional (3D) semiconductor memory device, comprising:
first and second semiconductor layers horizontally spaced apart from each other, on a substrate;
first and second cell array structures disposed on the first and second semiconductor layers, respectively; and
an isolation structure disposed on the substrate between the first and second cell array structures,
wherein the first cell array structure comprises:
an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and
a first source structure disposed between the first semiconductor layer and the electrode structure, and

the first source structure of the first cell array structure is horizontally extended onto an area of the substrate between the first and second semiconductor layers, and the first source structure of the first cell array structure and a second source structure of the second cell array structure are electrically separated from each other by the isolation structure.

15. The 3D semiconductor memory device of claim 14 , further comprising:
a third semiconductor layer on the substrate; and
a third cell array structure disposed on the third semiconductor layer,
wherein the first, second and third semiconductor layers are spaced apart from each other in a first direction and a second direction, which are parallel to a top surface of the substrate,
the isolation structure comprises a plurality of isolation structures,
a first one of the plurality of the isolation structures is disposed between the first and second cell array structures, which are adjacent to each other in the first direction,
a second one of the plurality of isolation structures is disposed between the first and third cell array structures, which are adjacent to each other in the second direction, and
the plurality of isolation structures are spaced apart from each other.

16. The 3D semiconductor memory device of claim 14 , further comprising:
third and fourth semiconductor layers horizontally spaced apart from each other, on the substrate; and
third and fourth cell array structures disposed on the third and fourth semiconductor layers, respectively,
wherein the first, second, third and fourth semiconductor layers are spaced apart from each other in a first direction and a second direction, which are parallel to a top surface of the substrate, and
the isolation structure is disposed between the first and second cell array structures, which are adjacent to each other in the first direction, and is extended into a region between the third and fourth cell array structures, which are adjacent to each other in the first direction.

17. The 3D semiconductor memory device of claim 14 , further comprising:
peripheral circuits disposed on the substrate; and
a lower insulating layer covering the peripheral circuits,
wherein the first and second semiconductor layers and the isolation structure are disposed on the lower insulating layer, and
the first and second source structures of the first and second cell array structures are horizontally extended onto the lower ins

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Jongseon
• Sim Jaeryong
• Chung Giyong
• Han Jeehoon

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title