Semiconductor device with vertical memory

Patent metadata

Field	Value
Publication number	US-9905570-B2
Application number	US-201615018477-A
Country	US
Kind code	B2
Filing date	Feb 8, 2016
Priority date	Nov 8, 2013
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a memory cell array region;
a memory cell array on the memory cell array region, the memory cell array including:
a channel layer extending in a vertical direction on the substrate, and
at least one ground selection line, at least one word line, and at least one string selection line spaced apart in the vertical direction along a sidewall of the channel layer;

at least one first p well outside the memory cell array region on the substrate; and
at least one buried contact between the at least one first p well and the substrate,
wherein the at least one first p well includes an impurity region doped with p-type impurities having a doping concentration that increases in a vertically downward direction toward the substrate.

2. The semiconductor device as claimed in claim 1 , further comprising a second p well formed on the substrate, the second p well being disposed under the memory cell array, and
wherein the at least one first p well is disposed outside the second p well.

3. A semiconductor device, comprising:
a substrate including a memory cell array region;
a memory cell array on the memory cell array region, the memory cell array including:
a channel layer extending in a vertical direction on the substrate, and
at least one ground selection line, at least one word line, and at least one string selection line spaced apart in the vertical direction along a sidewall of the channel layer; and

at least one first p well outside the memory cell array region on the substrate;
at least one buried contact between the at least one first p well and the substrate;
a second p well formed on the substrate, the second p well being disposed under the memory cell array; and
a common source region on the substrate, the common source region including an impurity region doped with n-type impurities having a doping concentration that increases in a vertically downward direction toward the substrate, and
wherein the common source region is disposed in the second p well.

4. The semiconductor device as claimed in claim 3 , wherein the common source region is spaced apart from the at least one first p well.

5. The semiconductor device as claimed in claim 1 , wherein the at least one first p well does not vertically overlap the memory cell array region.

6. The semiconductor device as claimed in claim 1 , wherein the buried contact is electrically connected between the at least one first p well and a connection structure, the connection structure being under the at least one first p well and above the substrate.

7. A semiconductor device, comprising:
a semiconductor layer formed on a substrate, the semiconductor layer including a plurality of first p well regions and a second p well region;
a memory cell array formed on the second p well region, the memory cell array including:
a channel layer extending in a vertical direction on the semiconductor layer, and
a ground selection line, a plurality of word lines and a string selection line spaced apart in the vertical direction along a sidewall of the channel layer; and

a buried contact on the substrate, the buried contact being electrically connected to at least one first p well region of the plurality of first p well regions, and the buried contact vertically overlapping the at least one first p well region of the plurality of first p well regions,
wherein the plurality of first p well regions is spaced apart from each other along an outer circumference of the second p well region.

8. The semiconductor device as claimed in claim 7 , wherein the plurality of first p well regions is disposed immediately adjacent to the second p well region.

9. The semiconductor device as claimed in claim 7 , wherein the plurality of first p well regions does not vertically overlap the memory cell array.

10. The semiconductor device as claimed in claim 7 , wherein a sidewall of the plurality of first p well regions contacts the second p well region.

11. The semiconductor device as claimed in claim 7 , further comprising a common source region on the substrate, the common source region including an impurity region doped with n-type impurities having a doping concentration that increases in a vertically downward direction toward the substrate, and
wherein the common source region is disposed in the second p well region.

12. The semiconductor device as claimed in claim 7 , further comprising barrier metal layer formed between the buried contact and the at least one first p well region of the plurality of first p well regions.

13. The semiconductor device as claimed in claim 12 , wherein the at least one first p well region of the plurality of first p well regions has a doping concentration profile in which a doping concentration increases along a direction toward the buried contact.

14. The semiconductor device as claimed in claim 1 , wherein the buried contact vertically overlaps the at least one first p well.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Yoo Cheol
• Park Young Woo
• Lee Jae Duk

Classifications

• H01L27/11526

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H01L27/11578 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L29/7889

  Electricity · mapped topic