Method of fabricating a three-dimensional semiconductor memory device having a plurality of memory blocks on a peripheral logic structure

Patent metadata

Field	Value
Publication number	US-9837429-B2
Application number	US-201615348009-A
Country	US
Kind code	B2
Filing date	Nov 10, 2016
Priority date	Oct 27, 2014
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

First claim

What is claimed is:

1. A method of fabricating a three-dimensional (3D) semiconductor memory device, the method comprising:
forming a peripheral logic structure comprising peripheral logic circuits on a semiconductor substrate; and
forming a plurality of memory blocks on the peripheral logic structure to be spaced apart from each other,
wherein each of the memory blocks comprises a stack structure including a plurality of vertically stacked electrodes on a semiconductor layer.

2. The method of claim 1 , wherein each of the memory blocks further comprises a well plate electrode between the peripheral logic structure and the semiconductor layer.

3. The method of claim 2 , wherein the semiconductor layer is in contact with the well plate electrode.

4. The method of claim 2 , wherein forming the peripheral logic structure comprises:
forming a voltage generator on the semiconductor substrate, and
forming an insulation layer to cover the voltage generator.

5. The method of claim 4 , wherein forming the peripheral logic structure further comprises forming an interconnection structure for electrically connecting the well plate electrode to the voltage generator.

6. The method of claim 4 , wherein the well plate electrode is formed on a top surface of the insulation layer.

7. The method of claim 6 , wherein the well plate electrode is formed to overlap with the interconnection structure.

8. The method of claim 1 , wherein forming the plurality of memory blocks comprises:
forming a well conductive layer on the peripheral logic structure and a poly-silicon layer on the well conductive layer; and
patterning the poly-silicon layer and the well conductive layer to form the semiconductor layers of the memory blocks and well plate electrodes that are respectively between the semiconductor layers and the peripheral logic structure.

9. The method of claim 1 , wherein forming the plurality of memory blocks includes:
forming a plurality of vertical structures penetrating the stack structure of each of the memory blocks; and
forming a plurality of bit lines crossing the stack structure and electrically connected to the vertical structures.

10. The method of claim 1 , wherein the stack structure has a stepwise structure defined by end portions of the electrodes.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Yunghwan
• Sim Jaesung
• Kang Shinhwan
• Park Youngwoo
• Lee Jaeduk

Classifications

• H10W90/00

  Package configurations · CPC title

• H01L27/11526

  Electricity · mapped topic

• G11C16/30

  Power supply circuits · CPC title

• H01L27/11551

  Electricity · mapped topic

• H01L27/11548

  Electricity · mapped topic