Three dimensional memory device having well contact pillar and method of making thereof

Patent metadata

Field	Value
Publication number	US-9768186-B2
Application number	US-201615216941-A
Country	US
Kind code	B2
Filing date	Jul 22, 2016
Priority date	Sep 19, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.

First claim

What is claimed is:

1. A monolithic three dimensional memory device, comprising:
a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate;
a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate;
a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member comprising an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region; and
a plurality of electrically conductive word lines extending substantially parallel to the major surface of the semiconductor substrate and adjacent to the support members, wherein the word lines comprise or are electrically continuous with a plurality of control gate electrodes of the NAND memory strings, the plurality of control gate electrodes comprising at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, wherein:
each of the plurality of NAND memory strings comprises a substantially pillar-shaped structure extending substantially perpendicular to the major surface of the semiconductor substrate, and each of the plurality of substantially-pillar shaped support members has a width that is greater than a width of the substantially pillar shaped NAND strings;
each of the NAND memory strings comprises:
a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to the major surface of the semiconductor substrate,
at least one charge storage region located adjacent to at least the first side surfaces of each of the control gate electrodes,
a blocking dielectric located adjacent to at least the first side surfaces of each of the control gate electrodes and located between the at least one charge storage region and each of the control gate electrodes, and
a tunnel dielectric located between the at least one charge storage region and the semiconductor channel;

the plurality of NAND strings and at least one support member are located in an active memory cell area of the memory device, wherein the active memory cell area is located between a pair of electrically conductive source lines extending in a first direction substantially parallel the major surface of the semiconductor substrate;
the doped well region comprises a p-well region; and
each of the source lines comprises a source electrode that is electrically coupled via a source region to the semiconductor channel of at least one NAND string by a semiconductor channel portion that extends substantially parallel to the major surface of the semiconductor substrate and contacts the semiconductor channel from below the device levels.

2. The monolithic three dimensional memory device of claim 1 , further comprising at least one drain electrode which contacts the semiconductor channel via a drain region from above the device levels, and at least one bit line which extends substantially perpendicular to the source electrode and which electrically contacts the at least one drain electrode.

3. The monolithic three dimensional memory device of claim 1 , further comprising:
at least one electrically conductive shunt line extending in a second direction substantially parallel to the major surface of the semiconductor substrate and to the at least one bit line, wherein the second direction is substantially perpendicular to the first direction of the source electrode, and wherein the electrically conductive core of each of the plurality of support members electrically contacts the doped well region at a first end of the core and is electrically coupled to a shunt line at a second end of the core opposite the first end.

4. The monolithic three dimensional memory device of claim 3 , wherein at least one support member is located between first and second sets of one or more NAND strings within the active memory cell area and the at least one support member extends through a plurality of vertically separated word line fingers under the at least one electrically conductive shunt line.

5. The monolithic three dimensional memory device of claim 4 , wherein at least one additional support member is further located in a word line connection region containing a plurality of word line contacts which contact respective stepped portions of the plurality of electrically conductive word lines.

6. The monolithic three dimensional memory device of claim 1 , wherein at least one support member is located in a word line connection region containing a plurality of word line contacts which contact respective stepped portions of the plurality of electrically conductive word lines.

7. The monolithic three dimensional memory device of claim 1 , wherein:
the substrate comprises a silicon substrate;
the plurality of NAND strings comprise a monolithic, three dimensional array of NAND strings;
at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings; and
the silicon substrate contains located thereon an integrated circuit comprising a driver circuit for the array of NAND strings.

8. A monolithic three dimensional memory device, comprising:
a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate;
a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate;
a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member comprising an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region; and
a plurality of electrically conductive word lines extending substantially parallel to the major surface of the semiconductor substrate and adjacent to the support members, wherein the word lines comprise or are electrically continuous with a plurality of control gate electrodes of the NAND memory strings, the plurality of control gate electrodes comprising at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, wherein:
each of the plurality of NAND memory strings comprises a substantially pillar-shaped structure extending substantially perpendicular to the major surface of the semiconductor substrate, and each of the plurality of substantially-pillar shaped support members has a width that is greater than a width of the substantially pillar shaped NAND strings; and
at least one substantially pillar-shaped support member among the plurality of substantially pillar-shaped support members is located in a word line connection region containing a plurality of word line contacts which contact respective stepped portions of the plurality of electrically conductive word lines.

9. The monolithic three dimensional memory devi

Assignees

• Sandisk Technologies Llc

Inventors

• Shimabukuro Seiji
• Honma Ryoichi
• Ogawa Hiroyuki
• Mizutani Yuki
• Toyama Fumiaki

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L29/7926

  Electricity · mapped topic

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• H01L27/11524

  Electricity · mapped topic

• H01L27/11556 Primary

  Electricity · mapped topic