Semiconductor fabrication with electrochemical apparatus

Patent metadata

Field	Value
Publication number	US-11101149-B2
Application number	US-202016933727-A
Country	US
Kind code	B2
Filing date	Jul 20, 2020
Priority date	Sep 27, 2017
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

A method includes depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately; patterning the first and second semiconductor layers to form a fin structure; supplying a first bias to the substrate after patterning the first and second semiconductor layers; and etching the second semiconductor layers when the semiconductor substrate is supplied with the first bias, wherein etching the second semiconductor layers is performed such that the first semiconductor layers are suspended above the substrate.

First claim

What is claimed is:

1. A method, comprising:
depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately;
patterning the first and second semiconductor layers to form a fin structure;
supplying a first bias to the substrate after patterning the first and second semiconductor layers; and
etching the second semiconductor layers when the substrate is supplied with the first bias, wherein etching the second semiconductor layers is performed such that the first semiconductor layers are suspended above the substrate.

2. The method of claim 1 , wherein etching the second semiconductor layers comprises:
immersing the substrate in an electrolyte bath, wherein the electrolyte bath comprises a semiconductor material the same as that of the first semiconductor layers.

3. The method of claim 1 , wherein the first bias is smaller than an oxidation potential of planes <110> and <100> of the first semiconductor layers.

4. The method of claim 1 , wherein the first bias is larger than an oxidation potential of planes <110> and <100> of the first semiconductor layers and smaller than an oxidation potential of a plane <111> of the first semiconductor layers.

5. The method of claim 1 , wherein the first bias is larger than an oxidation potential of a plane <111> of the first semiconductor layers.

6. The method of claim 1 , further comprising:
removing a surface oxide on one of the first semiconductor layers and the second semiconductor layers during depositing the first semiconductor layers and the second semiconductor layers over the substrate, wherein removing the surface oxide comprises:
immersing the substrate in an electrolyte bath; and
supplying a second bias to the substrate, wherein the second bias is negative.

7. A method, comprising:
depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately;
patterning the first and second semiconductor layers to form a fin structure;
immersing the substrate and the fin structure in an electrolyte bath; and
supplying a first bias to the substrate when the substrate and the fin structure are immersed in the electrolyte bath.

8. The method of claim 7 , wherein the electrolyte bath comprises an element the same as that of the first semiconductor layers.

9. The method of claim 7 , wherein immersing the substrate and the fin structure in the electrolyte bath is performed such that at least one of the first semiconductor layers is etched to have a bottom side, a top side, and an edge facet connecting the bottom side to the top side.

10. The method of claim 7 , wherein immersing the substrate and the fin structure in the electrolyte bath is performed such that at least one of the first semiconductor layers is etched to have a bottom side, a top side, and an edge side connecting the bottom side to the top side, wherein the edge side comprises an upper angled facet and a lower angled facet.

11. The method of claim 7 , wherein immersing the substrate and the fin structure in the electrolyte bath is performed such that at least one of the first semiconductor layers is etched to have a bottom end, a top end, a first edge side connecting the bottom end to the top end, and a second edge side connecting the bottom end to the top end and opposite to the first edge side, wherein at least one of the first edge side and the second edge side comprises an upper angled facet and a lower angled facet.

12. The method of claim 7 , wherein immersing the substrate and the fin structure in the electrolyte bath is performed such that at least one of the first semiconductor layers is etched to have a round configuration.

13. The method of claim 7 , wherein supplying the first bias to the substrate is performed to induce an oxidation reaction in the electrolyte bath.

14. The method of claim 7 , wherein supplying the first bias to the substrate comprises:
alternatively supplying the first bias and a second bias to the substrate to respectively induce oxidation and reduction reactions in the electrolyte bath, wherein the first bias is greater than the second bias.

15. A method, comprising:
patterning a semiconductor substrate to form a semiconductor fin;
forming an isolation structure surrounding the semiconductor fin;
etching a portion of the semiconductor fin such that a top surface of the portion of the semiconductor fin is lower than a top surface of the isolation structure; and
supplying a first bias to the semiconductor substrate during etching the portion of the semiconductor fin.

16. The method of claim 15 , further comprising:
depositing a plurality of first semiconductor layers and a plurality of second semiconductor layer over the semiconductor substrate, such that the first semiconductor layers and the second semiconductor layers are stacked alternately prior to patterning the semiconductor substrate to form the semiconductor fin.

17. The method of claim 15 , further comprising:
performing a cleaning process on the semiconductor substrate prior to patterning the semiconductor substrate to form the semiconductor fin, wherein the cleaning process comprises:
immersing the semiconductor substrate in an electrolyte bath; and
supplying a second bias to the semiconductor substrate when the semiconductor substrate is immersed in the electrolyte bath, wherein the second bias is negative.

18. The method of claim 17 , wherein the cleaning process is performed to remove a surface oxide from the semiconductor substrate.

19. The method of claim 15 , wherein supplying the first bias to the semiconductor substrate is performed to induce an oxidation reaction in an electrolyte bath.

20. The method of claim 15 , wherein supplying the first bias to the semiconductor substrate comprises:
alternatively supplying the first bias and a third bias to the semiconductor substrate to respectively induce oxidation and reduction reactions in an electrolyte bath, wherein the first bias is greater than the third bias.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kelly Andrew Joseph
• Oniki Yusuke

Classifications

• H10P14/6312

  of Group III-V semiconductors · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P50/617

  of Group III-V materials · CPC title

• H10P50/613 Primary

  of Group IV materials · CPC title