Semiconductor device for preventing defects between bit lines and channels

Patent metadata

Field	Value
Publication number	US-11049847-B2
Application number	US-202016734505-A
Country	US
Kind code	B2
Filing date	Jan 6, 2020
Priority date	May 17, 2019
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

A semiconductor device includes a first semiconductor structure comprising a substrate and a circuit element, and a second semiconductor structure connected to the first semiconductor structure. The second semiconductor structure includes a base layer, a first memory cell structure, a second memory cell structure, and common bit lines between the first memory cell structure and the second memory cell structure. The first memory cell structure includes first gate electrodes, first channel structures, and first string select channel structures. The second memory cell structure includes second gate electrodes, second channel structures, second string select channel structures, and connection regions between the second channel structures and the second string select channel structures. The first memory cell structure further includes first channel pads between the common bit lines and the first string select channel structures, and the second memory cell structure further includes second channel pads extending along the common bit lines.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor structure comprising a substrate and a circuit element on the substrate; and
a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure comprising:
a base layer;
a first memory cell structure comprising:
first gate electrodes on a first surface of the base layer, spaced apart from one another in a direction perpendicular to the first surface of the base layer;
first channel structures passing through a portion of the first gate electrodes; and
first string select channel structures connected to the first channel structures at one end of the first channel structures, the first string select channel structures passing through a portion of the first gate electrodes;

a second memory cell structure comprising:
second gate electrodes vertically overlapping the first gate electrodes and spaced apart from each other in the direction perpendicular to the first surface of the base layer;
second channel structures passing through a portion of the second gate electrodes;
second string select channel structures connected to the second channel structures at one end of the second channel structures, the second string select channel structures passing through a portion of the second gate electrodes; and
connection regions between the second channel structures and the second string select channel structures, the connection regions having a width wider than a width of the second channel structures and a width of the second string select channel structures; and

common bit lines between the first memory cell structure and the second memory cell structure, the common bit lines electrically connected to the first and second string select channel structures in common, wherein
the first memory cell structure further comprises first channel pads between the common bit lines and the first string select channel structures, and
the second memory cell structure further comprises second channel pads along the common bit lines on first surfaces of the common bit lines facing the second memory cell structure.

2. The semiconductor device according to claim 1 , wherein
the first channel pads are on second surfaces of the common bit lines, opposite to the first surfaces of the common bit lines, and confined to regions connected to the first string select channel structures.

3. The semiconductor device according to claim 1 ,
wherein the first string select channel structures comprise channel layers therein, and
wherein the first channel pads have a width substantially the same as a width of an outer wall of the channel layers in the first string select channel structures on an interface between the first channel pads and the first string select channel structures.

4. The semiconductor device according to claim 1 , wherein the second channel pads have a first thickness in a region not connected to the second string select channel structures, and a second thickness in a region connected to the second string select channel structures, the second thickness being less than the first thickness.

5. The semiconductor device according to claim 1 ,
wherein the common bit lines comprise conductive layers and barrier layers on the conductive layers, and
wherein the barrier layers are between the first and second channel pads and the conductive layers.

6. The semiconductor device according to claim 1 ,
wherein the first and second gate electrodes include first and second string select gate electrodes, respectively, adjacent to the common bit lines,
wherein the first and second string select channel structures pass through the first and second string select gate electrodes, and
wherein the first and second string select gate electrodes constitute string select transistors.

7. The semiconductor device according to claim 1 , wherein the first and second channel structures comprise gate dielectric layers and channel layers therein, sequentially arranged from the first and second gate electrodes, respectively,
wherein the channel layers extend from the first and second channel structures into the first and second string select channel structures, respectively.

8. The semiconductor device according to claim 1 , wherein the first and second channel pads are semiconductor layers containing impurities.

9. The semiconductor device according to claim 1 , wherein the first and second semiconductor structures further comprise first and second bonding pads bonded to each other.

10. The semiconductor device according to claim 6 ,
wherein the first and second string select gate electrodes comprise a material different from a material of the first and second gate electrodes constituting memory cells.

11. The semiconductor device according to claim 6 , wherein the second memory cell structure further comprises an etch stop layer surrounding a portion of the second string select channel structures adjacent to the connection regions.

12. The semiconductor device according to claim 7 , wherein, in the first memory cell structure, the gate dielectric layers do not extend into the first string select channel structures.

13. The semiconductor device according to claim 7 , wherein, in the first memory cell structure, the channel layers include a first horizontal portion extending in parallel with the first surface of the base layer, and intersecting the first channel structures in a region of the first channel structures adjacent to the first string select channel structures.

14. The semiconductor device according to claim 7 , wherein, in the second memory cell structure, the gate dielectric layers extend into the connection regions and do not extend into the second string select channel structures.

15. The semiconductor device according to claim 7 , wherein, in the second memory cell structure, the channel layers include a second horizontal portion extending in parallel with the first surface of the base layer, and intersecting the second string select channel structures in a region of the second string select channel structures adjacent to the connection regions.

16. The semiconductor device according to claim 7 ,
wherein the first and second string select channel structures further comprise gate insulation layers between the first and second gate electrodes and the channel layers, respectively, and
wherein the gate dielectric layers comprise a material different from a material of the gate insulation layers.

17. A semiconductor device comprising:
a base layer;
first gate electrodes on a first surface of the base layer, spaced apart from one another in a direction perpendicular to the first surface of the base layer;
first channel structures passing through at least a portion of the first gate electrodes, and including first channel layers;
second gate electrodes on one side of the first gate electrodes and spaced apart from each other in the direction perpendicular to the first surface of the base layer;
second channel structures passing through at least a portion of the second gate electrodes, and including second channel layers;
common bit lines between the first gate electrodes and the second gate electrodes and electrically connected to the first and second channel layers in common;
first channel pads between one end of the first channel structures and a first surface of the common bit lines; and
second channel pads along the common bit lines on second surfaces of the common bit lines, opposite to the first surface of the common bit lines.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kanamori Kohji
• Kim Yongseok
• Lee Kyunghwan
• Lim Junhee
• Han Jeehoon

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title