Three-dimensional memory device containing separately formed drain select transistors and method of making thereof

Patent metadata

Field	Value
Publication number	US-9922987-B1
Application number	US-201715468732-A
Country	US
Kind code	B1
Filing date	Mar 24, 2017
Priority date	Mar 24, 2017
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Memory stack structures can be formed through an alternating stack of insulating layers and spacer material layers that are formed as, or are subsequently replaced with, electrically conductive layers. The memory stack structures can be formed as rows having a first pitch. Additional insulating layers and at least one drain select level dielectric layer are formed over the alternating stack. Drain select level openings are formed in rows having a smaller second pitch. Partial replacement of the at least one drain select level dielectric layer forms spaced apart electrically conductive line structures that surround a respective plurality of drain select level openings. Drain select level channel portions are subsequently formed in respective drain select level openings.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
at least one drain select level conductive layer located over the alternating stack, wherein each of the at least one drain select level conductive layer comprises electrically conductive line structures that laterally extend along a first horizontal direction and are laterally spaced apart among one another along a second horizontal direction;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film; and
drain select level channel portions vertically extending through the at least one drain select level conductive layer, contacting a respective memory level channel portion, and laterally surrounded by a respective drain select level gate dielectric and a respective one of the electrically conductive line structures at each level of the at least one drain select level conductive layer;
wherein:
the memory stack structures are arranged in rows that extend along the first horizontal direction with a first row-to-row pitch along the second horizontal direction across an area including two or more electrically conductive line structures of a same drain select level;
for each electrically conductive line structure, a respective array of drain select level channel portions extends through the electrically conductive line structure, and drain select level channel portions within the respective array are arranged in at least four rows that extend along the first horizontal direction with a second row-to-row pitch along the second horizontal direction; and
the second row-to-row pitch is less than the first row-to-row pitch.

2. The three-dimensional memory device of claim 1 , wherein:
the drain select level channel portions within the respective array are arranged in four rows through each electrically conductive line structure; and
each of the electrically conductive line structures comprises a pair of sidewalls that generally extend along the first horizontal direction and including vertical convex surface portions that are adjoined among one another.

3. The three-dimensional memory device of claim 2 , further comprising additional insulating layers overlying the alternating stack, wherein:
each of the at least one drain select level conductive layer is located between a respective pair of the additional insulating layers; and
the insulating layers and the additional insulating layers comprise a first electrically insulating material.

4. The three-dimensional memory device of claim 3 , further comprising electrically insulating line structures that generally extend along the first horizontal direction and comprising a second electrically insulating material are located between each laterally neighboring pair of the electrically conductive line structures located at a same level.

5. The three-dimensional memory device of claim 4 , wherein each of the electrically insulating line structures comprises a pair of sidewalls that generally extend along the first horizontal direction and including vertical concave surface portions that are adjoined among one another.

6. The three-dimensional memory device of claim 1 , wherein:
the memory stack structures are arranged as a first periodic hexagonal array;
the respective array of drain select level channel portions is a respective second periodic hexagonal array; and
wherein the first periodic hexagonal array and each second periodic hexagonal array has a same periodicity along the first horizontal direction and different periodicities along the second horizontal direction.

7. The three-dimensional memory device of claim 1 , further comprising a pair of backside trenches vertically extending through the alternating stack and the at least one drain select level conductive layer and laterally extending along the first horizontal direction, wherein:
each of the electrically conductive layers within the alternating stack laterally extends continuously along the second horizontal direction between the pair of backside trenches; and
each of the electrically conductive line structures is located between the pair of backside trenches.

8. The three-dimensional memory device of claim 7 , wherein each of the pair of backside trenches comprises:
a lower backside trench vertically extending through the alternating stack and including a first conductive via structure including a metallic conductive material; and
an upper backside trench vertically extending through the at least one drain select level conductive layer and including a second conductive via structure comprising a same doped semiconductor material as the drain select level channel portions.

9. The three-dimensional memory device of claim 8 , further comprising:
an upper insulating spacer laterally surrounding the second conductive via structure;
a pair of electrically conductive rails contacting a respective sidewall of the upper insulating spacer and having a uniform vertical cross-sectional shape along the first horizontal direction; and
a pair of electrically insulating line structures contacting a respective one of the pair of electrically conductive line structures.

10. The three-dimensional memory device of claim 7 , wherein each of the pair of backside trenches comprises:
a lower backside trench vertically extending through the alternating stack and including a first insulating spacer;
an upper backside trench vertically extending through the at least one drain select level conductive layer and including an inner insulating spacer having a same thickness as the first insulating spacer and an outer insulating spacer contacting an outer sidewall of the inner insulating spacer; and
a conductive material portion that extends through the lower backside trench and the upper backside trench.

11. The three-dimensional memory device of claim 1 , wherein:
the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack;
the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and
support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces.

12. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending subst

Assignees

• Sandisk Technologies Llc

Inventors

• Mizutani Yuki
• Kai James
• Toyama Fumiaki
• Fujino Shigehiro
• Alsmeier Johann

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H01L27/11548 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic