Apparatuses and methods for forming multiple decks of memory cells

Patent metadata

Field	Value
Publication number	US-10079246-B2
Application number	US-201715849242-A
Country	US
Kind code	B2
Filing date	Dec 20, 2017
Priority date	Oct 8, 2014
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

First claim

What is claimed is:

1. A method comprising:
forming a first deck having alternating first conductor materials and first dielectric materials and a hole containing materials extending through the first conductor materials and the first dielectric materials;
removing a portion of at least one of the materials from a portion of the hole;
enlarging the portion of the hole to form an enlarged portion of the hole;
forming a sacrificial material in the enlarged portion of the hole; and
forming a second deck having alternating second conductor materials and second dielectric materials over the first deck.

2. The method of claim 1 , further comprising:
forming a second hole through the second conductor materials and the second dielectric materials, such that at least a portion of the sacrificial material is exposed through the second hole;
removing the sacrificial material; and
forming a third hole through the first and second decks, such that the third hole includes a combination of the second hole and the hole, including the enlarged hole portion of the hole.

3. The method of claim 2 , further comprising:
forming a tunneling material on sidewalls of the third hole; and
forming a channel material adjacent the tunneling material.

4. The method of claim 3 , further comprising:
forming a third dielectric material in the hole, the third dielectric material being surrounded by at least the channel material.

5. The method of claim 1 , further comprising:
forming a second hole through the second conductor materials and second dielectric materials, such that at least a portion of the sacrificial material is exposed at the second hole;
removing the sacrificial material;
forming a tunneling material on sidewalls of the second hole; and
forming a channel material adjacent the tunneling material and contacting an additional channel material in the hole.

6. The method of claim 5 , further comprising:
forming a third dielectric material in the hole, the third dielectric material being surrounded by at least the channel material adjacent the tunneling material.

7. The method of claim 1 , wherein the sacrificial material includes aluminum.

8. A method comprising:
forming a first deck having alternating first conductor materials and first dielectric materials and a first hole containing materials extending through the first conductor materials and the first dielectric materials, the materials in the first hole include a tunneling material on sidewalls of the first hole and an additional material adjacent the tunneling material;
removing a portion of the additional material from a portion of the first hole;
enlarging the portion of the first hole to form an enlarged portion of the first hole;
forming a sacrificial material in the enlarged portion of the first hole;
forming alternating levels of second conductor materials and second dielectric materials over the first deck;
forming a second hole to expose at least a portion of the sacrificial material in the first hole;
recessing the second conductor materials adjacent the second hole to form recesses;
forming a dielectric material on sidewalls of the second hole and on sidewalls of the recesses;
forming charge-storage material in the recesses and adjacent the dielectric material;
removing the sacrificial material;
forming an additional tunneling material in the second hole, such that the additional tunneling material contacts the tunneling material in the first hole;
removing a remaining portion of the additional material adjacent the tunneling material in first hole; and
forming a channel material on sidewalls of the first and second holes.

9. The method of claim 8 , wherein the tunneling material contained in the first hole includes an oxide of silicon, and the additional material contained in the first hole includes polysilicon.

10. The method of claim 8 , wherein the sacrificial material includes aluminum oxide.

Assignees

• Micron Technology Inc

Inventors

• Lu Zhenyu
• Lindsay Roger W
• Goda Akira
• Hopkins John

Classifications

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/04

  using variable threshold transistors, e.g. FAMOS · CPC title

• G11C16/0475

  comprising two or more independent storage sites which store independent data · CPC title