Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10672870-B2
Application number	US-201816036302-A
Country	US
Kind code	B2
Filing date	Jul 16, 2018
Priority date	Jul 16, 2018
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a fin structure over a substrate, the fin structure having a channel region and a source/drain region;
forming a gate structure over the channel region of the fin structure;
performing a first source/drain etching to recess the source/drain region of the fin structure;
after the first source/drain etching, performing a second source/drain etching to further recess the source/drain region of the fin structure;
after the second source/drain etching, performing a third source/drain etching to further recess the source/drain region of the fin structure, thereby forming a source/drain recess;
forming one or more epitaxial layers in the source/drain recess,
wherein the first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching,
wherein the one or more epitaxial layers include a first epitaxial layer and a second epitaxial layer formed on the first epitaxial layer,
wherein the first and second epitaxial layers comprise SiP or SiGe, and an amount of phosphorous or germanium in the second epitaxial layer is greater than an amount of phosphorous or germanium in the first epitaxial layer.

2. The method of claim 1 , wherein the third source/drain etching is isotropic etching.

3. The method of claim 2 , wherein:
the gate structure includes a gate dielectric layer disposed on the channel, a gate layer disposed on the gate dielectric layer and sidewall spacers disposed on opposing side faces of the gate layer, and
by the first source/drain etching, the source/drain region of the fin structure is laterally etched to a portion under the sidewall spacers.

4. The method of claim 3 , wherein by the first source/drain etching, the source/drain region of the fin structure is laterally etched to not reach a portion under the gate layer.

5. The method of claim 3 , wherein in the second source/drain etching, an amount of vertical etching is 10 times or more an amount of lateral etching.

6. The method of claim 3 , wherein by the third source/drain etching, the source/drain region of the fin structure is laterally etched to not reach a portion under the gate layer.

7. The method of claim 2 , wherein:
after the third source/drain etching the source/drain recess has a first width, a second width smaller than the first width and a third width greater than the second width, and
the second width is located between the first width and the third width in a vertical direction of the source/drain recess.

8. The method of claim 7 , wherein the first width is a largest width of the source/drain recess.

9. The method of claim 8 , wherein the first width is located at a level below a top of the channel region by an amount D, where 0<D<0.2×L, L is a depth of the source/drain recess.

10. The method of claim 8 , wherein the source/drain recess has a largest width at a level below a top of the channel region by an amount D, where 0<D<0.2×L, L is a depth of the source/drain recess.

11. The method of claim 3 , wherein:
the second epitaxial layer does not penetrate the portion under the sidewall spacers.

12. The method of claim 11 , wherein a top of the second epitaxial layer is located above a level of a top of the channel region of the fin structure.

13. The method of claim 3 , wherein:
the sidewall spacers includes first sidewall spacer layers and second sidewall spacer layer disposed over the first sidewall spacer layers, and
by the first source/drain etching, the source/drain region of the fin structure is laterally etched to a portion under the second sidewall spacers.

14. The method of claim 13 , wherein by the first source/drain etching, the source/drain region of the fin structure is laterally etched to not reach a portion under the first sidewall spacer layers.

15. The method of claim 13 , wherein by the third source/drain etching, the source/drain region of the fin structure is laterally etched to not reach a portion under the first sidewall spacer layers.

16. A method of manufacturing a semiconductor device, the method comprising:
forming a fin structure over a substrate, the fin structure having a channel region;
forming gate structures over the channel region of the fin structure;
performing a first source/drain etching to recess a source/drain region of the fin structure disposed between the gate structures;
after the first source/drain etching, performing a second source/drain etching to further recess the source/drain region of the fin structure;
after the second source/drain etching, performing a third source/drain etching to further recess the source/drain region of the fin structure, thereby forming a source/drain recess;
forming a first epitaxial layer and a second epitaxial layer over the first epitaxial layer in the source/drain recess, wherein:
the first and second epitaxial layers are made of SiP or SiGe,
an amount of phosphorous or germanium in the second epitaxial layer is greater than an amount of phosphorous or germanium in the first epitaxial layer,
the first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching,
the gate structure includes a gate dielectric layer disposed on the channel, a gate layer disposed on the gate dielectric layer and sidewall spacers disposed on opposing side faces of the gate layer, and
the first epitaxial layer is in contact with a bottom of the sidewall spacers and not in contact with side faces of the sidewall spacers.

17. The method of claim 16 , wherein the second epitaxial layer is not in contact with the bottom of the sidewall spacers and is in contact with the side faces of the sidewall spacers.

18. A semiconductor device comprising:
a gate structure including a gate dielectric layer disposed over a channel region of a fin structure and a gate electrode disposed over the gate dielectric layer;
sidewall spacers disposed on opposing side faces of the gate structure;
a source/drain epitaxial layer comprising SiP, SiCP, SiC, SiGe, SiGeSn, or SiGeB formed in a source/drain region of the fin structure, wherein
the source/drain epitaxial layer has a first width, a second width smaller than the first width and a third width greater than the second width, and
the first width is located below a top of the channel region of the fin structure, and the second width is located between the first width and the third width in a vertical direction of the source/drain epitaxial layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Lung
• Kuo Kang-Min
• Hong Long-Jie

Classifications

• H01L29/165

  Electricity · mapped topic

• H01L21/823814

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic

• H01L29/0847 Primary

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic