Integrated standard cell structure

Patent metadata

Field	Value
Publication number	US-10276554-B1
Application number	US-201816008563-A
Country	US
Kind code	B1
Filing date	Jun 14, 2018
Priority date	Jun 14, 2018
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and having a one-pitch dimension P. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region. The first filler cell includes a third dielectric gate on a first filler cell boundary and a fourth dielectric gate on a second filler cell boundary.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first standard cell having a first p-type field-effect transistor (pFET) and a first n-type field-effect transistor (nFET) integrated, and having a first dielectric gate on a first standard cell boundary;
a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary; and
a first filler cell configured between the first and second standard cells, and having a one-pitch dimension P, wherein
the first pFET and the second pFET are formed on a first continuous active region,
the first nFET and the second nFET are formed on a second continuous active region, and
the first filler cell includes a third dielectric gate on a first filler cell boundary and a fourth dielectric gate on a second filler cell boundary.

2. The integrated circuit of claim 1 , wherein the first filler cell adjoins the first standard cell on the third dielectric gate and adjoins the second standard cell on the fourth dielectric gate.

3. The integrated circuit of claim 1 , wherein
the first filler cell spans the one-pitch dimension P from the first filler cell boundary to the second filler cell boundary along a first direction;
the first standard cell spans a first dimension D 1 along the first direction; and
the second standard cell spans a second dimension D 2 along the first direction, wherein D 2 =D 1 >2*P.

4. The integrated circuit of claim 3 , wherein each of the first, second, third and fourth dielectric gates is a dielectric feature extending along a second direction being orthogonal to the first direction and disposed directly on the first and second continuous active regions.

5. The integrated circuit of claim 4 , wherein
the first standard cell further includes a first gate stack extending, along the second direction, from the first continuous active region to the second continuous active region; and
the second standard cell further includes a second gate stack extending, along the second direction, from the first continuous active region to the second continuous active region.

6. The integrated circuit of claim 5 , wherein
the first gate stack is spaced a first distance from the first dielectric gate and is spaced a second distance from the third dielectric gate;
the second gate stack is spaced a third distance from the second dielectric gate and is spaced a fourth distance from the fourth dielectric gate; and
the first, second, third and fourth distances all equal to P.

7. The integrated circuit of claim 6 , wherein D 2 =D 1 =2*P.

8. The integrated circuit of claim 5 , wherein
the first standard cell further includes a third gate stack directly on the first continuous active region and a fifth dielectric gate on the second continuous active region, wherein the third gate stack extends along the second direction to contact the fifth dielectric gate; and
the second standard cell further includes a sixth dielectric gate on the first continuous active region and a fourth gate stack directly on the second continuous active region, wherein the sixth dielectric gate extends along the second direction to contact the fourth gate stack.

9. The integrated circuit of claim 1 , further comprising a second filler cell between the first and second standard cells, wherein
the second filler cell includes a fifth dielectric gate;
the second filler cell adjoins the first filler cell on the fourth dielectric gate and adjoins the second standard cell on the fifth dielectric gate;
the second filler spans the one-pitch dimension P from the fourth dielectric gate to the fifth dielectric gate; and
the first and second continuous active regions extend through the first and second filler cells.

10. The integrated circuit of claim 1 , further comprising
a third standard cell having a third pFET and a third nFET integrated, and having a fifth dielectric gate on a third standard cell boundary; and
a second filler cell configured between the second and third standard cells, wherein
the second filler cell spans the one-pitch dimension P, along the first direction, from the second dielectric gate to a sixth dielectric gate on a third filler cell boundary;
the third pFET is formed on the first continuous active region;
the third nFET is formed on the second continuous active region;
the third standard cell adjoins the second filler cell on the sixth dielectric gate; and
the third standard cell spans along the first direction, from the fifth dielectric gate to the sixth dielectric gate, a dimension at least equal to 2*P.

11. The integrated circuit of claim 1 , wherein
the first continuous active region is enclosed in an n-type doped well; and
the second continuous active region is enclosed in a p-type doped well.

12. An integrated circuit, comprising:
a first standard cell having a first gate stack, a second gate stack, a first dielectric gate on a first standard cell boundary, and a second dielectric gate contacting the second gate stack;
a second standard cell having a third gate stack, a fourth gate stack, a third dielectric gate on a second standard cell boundary, and a fourth dielectric gate contacting the fourth gate stack;
a first filler cell disposed between the first and second standard cells, and spanning from a fifth dielectric gate and a sixth dielectric gate;
a first continuous active region extending through the first standard cell, the first filler cell and the second standard cell along a first direction; and
a second continuous active region extending through the first standard cell, the first filler cell and the second standard cell along the first direction, wherein
the first filler cell adjoins the first standard cell on the fifth dielectric gate and adjoins the second standard cell on the sixth dielectric gate; and
each of the first gate stack, the third gate stack, the first dielectric gate, the third dielectric gate, the fifth dielectric gate, and the sixth dielectric gate is extending, along a second direction being orthogonal to the first direction, from the first continuous active region to the second continuous active region.

13. The integrated circuit of claim 12 , wherein
the first filler cell spans an one-pitch dimension P from the fifth dielectric gate to the sixth Dielectric gate along the first direction;
the first standard cell spans a first dimension D 1 along the first direction; and
the second standard cell spans a second dimension D 2 along the first direction, wherein D 2 =D 1 >2*P.

14. The integrated circuit of claim 12 , wherein
the second gate stack and the fourth dielectric gate are formed directly on the first continuous active region; and
the second dielectric gate and the fourth gate stack are formed directly on the second continuous active region.

15. The integrated circuit of claim 12 , wherein
the second gate stack and the fourth gate stack are formed directly on the first continuous active region; and
the second dielectric gate and the fourth dielectric gate are formed directly on the second continuous active region.

16. The integrated circuit of claim 12 , wherein
each of the first, second, third, fourth, fifth, and sixth dielectric gates is a dielectric feature; and
each of the first, second, third, and fourth gate stacks includes a gate dielectric layer and a gate electrode.

17. The integrated circuit of claim 12 , wherein
the first continuous active region is enclosed in an n-type doped well; and
the second continuous act

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Fang
• Liaw Jhon Jhy

Classifications

• H01L27/0207 Primary

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic

• H10D30/00

  Field-effect transistors [FET] (insulated-gate bipolar transistors H10D12/00) · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title