System and method for lithography alignment

Patent metadata

Field	Value
Publication number	US-9304403-B2
Application number	US-201313732913-A
Country	US
Kind code	B2
Filing date	Jan 2, 2013
Priority date	Jan 2, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

The present disclosure provides one embodiment of a lithography system for integrated circuit making. The system includes a substrate stage designed to secure a substrate and being operable to move the substrate; an alignment module that includes a tunable light source being operable to generate an infrared light with a wavelength tunable; and a detector to receive the light; and an exposing module integrated with the alignment module and designed to performing an exposing process to a resist layer coated on the substrate.

First claim

What is claimed is:

1. A method, comprising:
providing an integrated circuit (IC) substrate having a first alignment mark, a second alignment mark, and a first circuit pattern defined in a first pattern layer and a third alignment mark, a fourth alignment mark, and a second circuit pattern defined in a second pattern layer;
illuminating the first and second alignment marks, through a photomask, with a first light to determine a first layer alignment error including a first alignment error in relation to the first alignment mark and a second alignment error in relation to the second alignment mark, wherein the first alignment error has more weight than the second alignment error;
illuminating the third and fourth alignment marks, through the photomask, with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to fourth alignment mark, wherein the third alignment error has more weight than the fourth alignment error;
determining a collective alignment error including the first layer alignment error in relation to the first circuit pattern and the second layer alignment error in relation to the second circuit pattern; and
adjusting alignment between the IC substrate and the photomask to minimize the collective alignment error.

2. The method of claim 1 , further comprising tuning a first wavelength of the first light according to pattern topography and pattern contrast of the first alignment mark before the illuminating of the first alignment mark.

3. The method of claim 1 , further comprising
identifying the third alignment mark according to orientation sensitivity of the second circuit pattern; and
tuning a second wavelength of the second light according to pattern topography and pattern contrast of the third alignment mark before the illuminating of the third alignment mark.

4. The method of claim 1 , further comprising:
tuning a first wavelength of the first light based on contrast and topography of the first circuit pattern; and
tuning a second wavelength of the second light based on contrast and topography of the second circuit pattern.

5. The method of claim 1 , further comprising:
depositing a third layer over the first pattern layer and the second pattern layer;
forming a sensitive resist layer over the third layer; and
after adjusting alignment between the IC substrate and the photomask, patterning the third layer to form a third circuit pattern using the photomask.

6. The method of claim 5 , wherein the adjusting alignment between the IC substrate and the photomask further comprises:
adjusting alignment between the IC substrate and the photomask to align a first set of contacts defined by the third circuit pattern with active regions defined by the first circuit pattern and to align a second set of contacts defined by the third circuit pattern with gates defined by the second circuit pattern.

7. The method of claim 1 , wherein the first alignment mark is designed to monitor alignment in a first direction, and wherein the second alignment mark is designed to monitor alignment in a second direction perpendicular to the first direction.

8. A method, comprising:
providing a first layer having a first alignment mark designed to monitor alignment in a first direction, a second alignment mark designed to monitor alignment in a second direction, and a first circuit pattern;
providing a second layer disposed over the first layer, wherein the second layer includes a third alignment mark designed to monitor alignment in a third direction, a fourth alignment mark designed to monitor alignment in a fourth direction, and a second circuit pattern;
performing a first alignment measurement, using a photomask, to the first layer using a first light to determine a first alignment error, wherein the first alignment measurement has a higher measurement quality in the first direction than in the second direction;
performing a second alignment measurement, using the photomask, to the second layer using a second light to determine a second alignment error, wherein the second alignment measurement has a higher measurement quality in the third direction than in the fourth direction;
determining a collective alignment error including the first alignment error in relation to the first circuit pattern and the second alignment error in relation to the second circuit pattern; and
adjusting alignment between the IC substrate and the photomask to minimize the collective alignment error.

9. The method of claim 8 , further comprising:
tuning a first wavelength of the first light from a tunable light source according to the first alignment mark before the performing the first alignment measurement; and
tuning a second wavelength of the second light from the tunable light source according to the third alignment mark before the performing the second alignment measurement.

10. The method of claim 9 , further comprising:
depositing a third layer over the first layer and the second layer;
forming a sensitive resist layer over the third layer; and
after the adjusting alignment between the IC substrate and the photomask, patterning the third layer to form a third circuit pattern using the photomask.

11. The method of claim 10 , wherein the first circuit pattern includes active regions aligned in a direction perpendicular to the first direction, wherein the second circuit pattern includes gates aligned in a direction perpendicular to the third direction, and wherein the adjusting alignment between the IC substrate and the photomask further comprises:
adjusting alignment between the IC substrate and the photomask to align a first set of contacts defined by the third circuit pattern with the active regions of the first circuit pattern and to align a second set of contacts defined by the third circuit pattern with the gates of the second circuit pattern.

12. The method of claim 11 , wherein the first circuit pattern and the second circuit pattern are used to form fin-like field-effect transistors (FinFETs) having the active regions and the gates.

13. The method of claim 9 , wherein the second direction is perpendicular to the first direction, and the fourth direction is perpendicular to the third direction.

14. The method of claim 9 , wherein the tunable light source is designed with a mechanism of tuning the first wavelength of the first light and the second wavelength of the second light, wherein the mechanism includes one of grating distributed Bragg reflector and optical cavity with a microelectromechanical system (MEMS) to tune a cavity length.

15. A method, comprising:
patterning a first layer over an integrated circuit (IC) substrate to form a first alignment mark, a second alignment mark, and a first circuit pattern;
disposing a second layer over the first layer;
patterning the second layer to form a third alignment mark, a fourth alignment mark, and a second circuit pattern;
illuminating the first and second alignment marks, through a photomask, with a first light to determine a first layer alignment error including a first alignment error in relation to the first alignment mark and a second alignment error in relation to the second alignment mark, wherein the first alignment error has more weight than the second alignment error;
illuminating the third and fourth alignment marks, through the photomask, with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to fourth align

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Lin Yu-Hsien
• Hsieh Hung-Chang
• Shiu Feng-Jia
• Lee Chun-Yi

Classifications

• G03F9/7084

  Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels · CPC title

• G03F7/70833

  Mounting of optical systems, e.g. mounting of illumination system, projection system or stage systems on base-plate or ground · CPC title

• G03F7/70716

  Stages · CPC title

• G03F7/70141 Primary

  Illumination system adjustment, e.g. adjustments during exposure or alignment during assembly of illumination system · CPC title

• H10P76/2041 Primary

  Photolithographic processes · CPC title