Methods, apparatus, and system for using filler cells in design of integrated circuit devices

Patent metadata

Field	Value
Publication number	US-9547741-B2
Application number	US-201414518939-A
Country	US
Kind code	B2
Filing date	Oct 20, 2014
Priority date	Oct 20, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.

First claim

What is claimed is:

1. A method for providing a layout for an integrated circuit device, comprising:
receiving a design for an integrated circuit device, wherein said design comprises
a first functional cell and a second functional cell;
placing said first functional cell on a circuit layout;
determining whether said first cell comprises a vertical boundary that is electrically floating;
placing a filler cell adjacent to said vertical boundary on said circuit layout in response to determining that said first cell comprises said vertical boundary that is electrically floating;
placing said second functional cell adjacent to said filler cell to form a contiguous active area on said circuit layout,
fabricating, by a semiconductor device processing system, said integrated circuit device based upon said circuit layout.

2. The method of claim 1 , wherein fabricating said integrated circuit based upon said circuit layout comprises fabricating at least one of a transistor, a capacitor, a resistor, a memory cell, or a processor.

3. The method of claim 1 , wherein said determining whether said first cell comprises a vertical boundary that is electrically floating comprises determining whether said first cell comprises a circuit element that is not electrically tied to at least one of ground or power.

4. The method of claim 3 , wherein determining whether said first cell comprises a circuit element that is not electrically tied to at least one of ground or power comprises determining whether said first element comprises a dummy gate of a transistor that is electrically tied to at least one of ground or power.

5. The method of claim 1 , wherein placing said filler cell adjacent to said vertical boundary comprises placing a filler cell that comprises a circuit element that is tied to at least one of ground or power at each of the vertical boundaries of said filler cell.

6. The method of claim 5 , placing said filler cell that comprises a circuit element that is tied to at least one of ground or power at each of the vertical boundaries comprises placing said filler cell that comprises a dummy gate that is tied to at least one of ground or power at each of the vertical boundaries of said filler cell.

7. The method of claim 1 , further comprising:
converting said first functional cell into a first contiguous active area; and
converting said second functional cell into a second contiguous active area.

8. The method of claim 7 , further comprising providing said first contiguous active area and said second contiguous active area into a circuit layout for fabricating said integrated circuit device.

9. The method of claim 1 , further comprising:
converting said first functional cell into a first contiguous active area and storing said first contiguous active area into a design library that is accessible for generating a design; and
converting said second functional cell into a second contiguous active area and storing said first contiguous active area into a design library that is accessible for generating a design.

10. The method of claim 1 , wherein placing a filler cell adjacent to said vertical boundary on said circuit layout further comprises selecting one of a plurality of filler cells for placing based upon at least one characteristic of said vertical boundary of said first functional cell.

11. The method of claim 1 , wherein placing said filler cell comprises placing a filler cell that has a dimension of one contacted poly pitch (CPP).

12. An apparatus for providing a design for and fabricating an integrated circuit device, the apparatus comprising:
an integrated circuit design unit adapted to:
place a first functional cell on a circuit layout;
determine a first characteristic of a vertical boundary of said first functional cell;
select a first filler cell from a plurality of filler cells based upon said first characteristic;
place said first filler cell adjacent to said first functional cell to provide an electrical isolation between said first filler cell and said first functional cell for providing a first contiguous active area on said circuit layout, and

a semiconductor device processing system adapted to fabricate an integrated circuit device based upon said circuit layout.

13. The apparatus of claim 12 , further comprising a library that comprises said first functional cell and said plurality of filler cells, and wherein said library comprises a continuous active area layout.

14. The apparatus of claim 12 , wherein said integrated circuit design unit is further configured to place a second function cell adjacent to said first filler cell to provide an electrical isolation between said first filler cell and said second functional cell for providing a second contiguous active area on said circuit layout.

15. The apparatus of claim 14 , wherein said integrated circuit design unit is configured to provide a design output comprising said circuit for fabricating an integrated circuit device.

16. The apparatus of claim 12 , wherein said first characteristic is indicative of a circuit component at a vertical boundary of said first function cell being electrically floating.

17. A system, comprising:
an integrated circuit design unit adapted to:
place a first functional cell on a circuit layout;
determine a first characteristic of a vertical boundary of said first functional cell;
select a first filler cell from a plurality of filler cells based upon said first characteristic; and
place said first filler cell adjacent to said first functional cell to provide an electrical isolation between said first filler cell and said first functional cell for providing a first contiguous active area on said circuit layout;

a semiconductor device processing system adapted to fabricating an integrated circuit device based upon said circuit layout; and
a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system.

18. The system of claim 7 , wherein said first characteristic is indicative of a circuit component at a vertical boundary of said first function cell being electrically floating.

19. The system of claim 18 , wherein said integrated circuit design unit is further configured to place a second function cell adjacent to said first filler cell to provide an electrical isolation between said first filler cell and said second functional cell for providing a second contiguous active area on said circuit layout.

Assignees

• Globalfoundries Inc

Inventors

• Schroeder Uwe Paul
• Davar Sushama

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2111/20

  Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules · CPC title