FinFET and method of forming same

Patent metadata

Field	Value
Publication number	US-10269908-B2
Application number	US-201816041987-A
Country	US
Kind code	B2
Filing date	Jul 23, 2018
Priority date	Aug 2, 2016
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

A FinFET device and a method of forming the same are provided. A method includes forming a patterned mask stack over a substrate, features of the patterned mask stack protecting the substrate having a uniform width. Unprotected portions of the substrate exposed by the patterned mask stack are removed to form a plurality of recesses in the substrate, unremoved portions of the substrate interposed between adjacent recesses forming a plurality of fins. Portions of the plurality of fins are removed, a width of a first fin of the plurality of fins being less than a width of a second fin of the plurality of fins.

First claim

What is claimed is:

1. A structure comprising:
a base structure;
a first fin extending away from a top surface of the base structure, a top portion of the first fin having a first width, the first fin having a first faceted top surface;
a second fin extending away from the top surface of the base structure, the second fin being adjacent the first fin, a top portion of the second fin having a second width, the second fin having a second faceted top surface; and
a third fin extending away from the top surface of the base structure, the third fin being interposed between the first fin and the second fin, a top portion of the third fin having a third width, the third width being less than the first width and the second width.

2. The structure of claim 1 , wherein the first fin has a first sidewall and a second sidewall, wherein the first sidewall is opposite the second sidewall, and wherein a first slope of the first sidewall is different from a second slope of the second sidewall.

3. The structure of claim 1 , wherein the second fin has a first sidewall and a second sidewall, wherein the first sidewall is opposite the second sidewall, and wherein a first slope of the first sidewall is different from a second slope of the second sidewall.

4. The structure of claim 1 , wherein the third fin has a first sidewall and a second sidewall, wherein the first sidewall is opposite the second sidewall, and wherein a first slope of the first sidewall is approximately same as a second slope of the second sidewall.

5. The structure of claim 1 , wherein the first fin has a first height, the second fin has a second height and the third fin has a third height, and wherein the third height is less than the first height and the second height.

6. The structure of claim 5 , wherein the first height is substantially same as the second height.

7. The structure of claim 1 , wherein the first fin, the second fin and the third fin have a same height.

8. A structure comprising:
a semiconductor base structure;
a first semiconductor fin extending away from a top surface of the semiconductor base structure, the first semiconductor fin having a first height, the first semiconductor fin having a first faceted surface, wherein the first semiconductor fin has a first sidewall and a second sidewall, wherein the first sidewall is opposite the second sidewall, and wherein a first slope of the first sidewall is different from a second slope of the second sidewall;
a second semiconductor fin extending away from the top surface of the semiconductor base structure, the second semiconductor fin being adjacent the first semiconductor fin, the second semiconductor fin having a second height, the second semiconductor fin having a second faceted top surface; and
a third semiconductor fin extending away from the top surface of the semiconductor base structure, the third semiconductor fin being interposed between the first semiconductor fin and the second semiconductor fin, the third semiconductor fin having a third height, the third height being less than or equal to the first height and the second height.

9. The structure of claim 8 , wherein the second semiconductor fin has a third sidewall and a fourth sidewall, wherein the third sidewall is opposite the fourth sidewall, and wherein a third slope of the third sidewall is different from a fourth slope of the fourth sidewall.

10. The structure of claim 8 , wherein the third semiconductor fin has a third sidewall and a fourth sidewall, wherein the third sidewall is opposite the fourth sidewall, and wherein a third slope of the third sidewall is approximately same as a fourth slope of the fourth sidewall.

11. The structure of claim 8 , wherein a top portion of the first semiconductor fin has a first width, a top portion of the second semiconductor fin has a second width and a top portion of the third semiconductor fin has a third width, and wherein the third width is less than the first width and the second width.

12. The structure of claim 8 , wherein the semiconductor base structure, the first semiconductor fin, the second semiconductor fin and the third semiconductor fin comprise a same semiconductor material.

13. The structure of claim 8 , further comprising a gate stack over the first semiconductor fin, the second semiconductor fin and the third semiconductor fin.

14. The structure of claim 8 , wherein the third height is less than the first height and the second height.

15. A structure comprising:
a base structure;
a first semiconductor strip over the base structure, a bottom portion of the first semiconductor strip having a first width, the first semiconductor strip having a first sidewall and a second sidewall, the first sidewall being opposite the second sidewall, a first slope of the first sidewall being different from a second slope of the second sidewall;
a second semiconductor strip over the base structure, the second semiconductor strip being adjacent the first semiconductor strip, a bottom portion of the second semiconductor strip having a second width; and
a third semiconductor strip over the base structure, the third semiconductor strip being interposed between the first semiconductor strip and the second semiconductor strip, a bottom portion of the third semiconductor strip having a third width, the third width being less than the first width and the second width, the third semiconductor strip having a third sidewall and a fourth sidewall, the third sidewall being opposite the fourth sidewall, a third slope of the third sidewall being substantially same as a fourth slope of the fourth sidewall.

16. The structure of claim 15 , wherein the first semiconductor strip has a first height, the second semiconductor strip has a second height and the third semiconductor strip has a third height, and wherein the third height is less than the first height and the second height.

17. The structure of claim 15 , wherein the first semiconductor strip, the second semiconductor strip and the third semiconductor strip have a same height.

18. The structure of claim 15 , wherein the second semiconductor strip has a fifth sidewall and a sixth sidewall, the fifth sidewall being opposite the sixth sidewall, a fifth slope of the fifth sidewall being different from a sixth slope of the sixth sidewall.

19. The structure of claim 15 , wherein the first semiconductor strip having a first faceted top surface.

20. The structure of claim 19 , wherein the second semiconductor strip having a second faceted top surface.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Cheng
• Lin Chih-Han
• Tseng Horng-Huei

Classifications

• H01L29/0603

  Electricity · mapped topic

• H01L29/41791 Primary

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic