Passivated and faceted for fin field effect transistor

Patent metadata

Field	Value
Publication number	US-9287262-B2
Application number	US-201314051033-A
Country	US
Kind code	B2
Filing date	Oct 10, 2013
Priority date	Oct 10, 2013
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.

First claim

What is claimed is:

1. A method of forming a fin field effect transistor (FinFET), the method comprising:
forming one or more fins extending from a substrate, each of the one or more fins having one or more semiconductor layers overlying the substrate, each of the one or more fins having a lattice constant different than a lattice constant of an underlying layer;
forming a first passivation layer over the one or more fins;
after forming the first passivation layer, forming isolation regions along opposing sidewalls of the one or more fins, the one or more fins extending above an uppermost surface of the isolation regions;
reshaping exposed portions of the one or more fins; and
forming a second passivation layer over the reshaped exposed portions of the one or more fins.

2. The method of claim 1 , wherein the forming the one or more fins comprises:
forming one or more layers of semiconductor material on the substrate, each of the one or more layers of semiconductor material having a lattice constant different than adjoining layers; and
etching the one or more layers of semiconductor material, thereby forming the one or more fins.

3. The method of claim 2 , wherein the etching comprises etching a portion of the substrate.

4. The method of claim 1 , wherein the one or more semiconductor layers comprises a first semiconductor layer and a second semiconductor layer, the isolation regions extending to an interface between the first semiconductor layer and the second semiconductor layer.

5. The method of claim 1 , wherein the one or more semiconductor layers comprises a single semiconductor layer, the second passivation layer extending over sidewalls and a top surface of the single semiconductor layer.

6. The method of claim 1 , wherein the first passivation layer comprises an oxynitride.

7. The method of claim 1 , wherein the second passivation layer comprises an oxynitride.

8. The method of claim 1 , wherein the one or more semiconductor layers comprises a silicon germanium layer on the substrate and a germanium layer on the silicon germanium layer, and wherein the first passivation layer comprises silicon germanium oxynitride and the second passivation comprises germanium oxynitride.

9. The method of claim 1 , wherein the one or more semiconductor layers comprises a Si x1 Ge y1 layer on the substrate and a Si x2 Ge y2 layer on the Si x1 Ge y1 , wherein x1 differs from x2 and y1 differs from y2.

10. The method of claim 1 , wherein the one or more semiconductor layers comprises a silicon germanium layer on the substrate, the second passivation layer extending along sidewalls and an uppermost surface of the silicon germanium layer.

11. A method of forming a fin field effect transistor (FinFET), the method comprising:
forming a first passivation layer over a fin on a substrate, wherein the fin comprises a plurality of semiconductor layers having different lattice structures;
after forming the first passivation layer, forming isolation regions along opposing sidewalls of the fin, an upper portion of the fin extending above an uppermost surface of the isolation regions; and
reshaping the upper portion of the fin to form a reshaped portion of the fin.

12. The method of claim 11 , wherein the upper portion of the fin comprises a single semiconductor material.

13. The method of claim 11 , wherein forming the first passivation layer comprises forming a nitride layer over the fin.

14. The method of claim 11 , further comprising forming a second passivation layer over the upper portion of the fin after the reshaping.

15. The method of claim 11 , wherein the isolation regions have a planar upper surface.

16. A method of forming a fin field effect transistor (FinFET), the method comprising:
forming a fin over a substrate, the fin having at least one semiconductor layer having a different lattice constant than a lattice constant of the substrate;
forming a first passivation layer over the fin;
after forming the first passivation layer, forming isolation regions along opposing sidewalls of the fin, an exposed portion of the fin being free of the isolation regions;
reshaping the exposed portion of the fin; and
forming a gate electrode over the exposed portion of the fin.

17. The method of claim 16 , further comprising forming a second passivation layer over the fin prior to forming the gate electrode.

18. The method of claim 16 , wherein the fin comprises a first silicon germanium layer over the substrate.

19. The method of claim 18 , wherein the fin comprises a second silicon germanium layer over the first silicon germanium layer.

20. The method of claim 18 , wherein the fin comprises a germanium layer over the first silicon germanium layer.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chen Yen-Yu
• Shih Chi-Yuan
• Liu Chi-Wen

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/43

  comprising oxides, nitrides or carbides, e.g. ceramics or glasses · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D84/834

  comprising FinFETs · CPC title