Manufacturing method for forming semiconductor structure with sub-fin structures

Patent metadata

Field	Value
Publication number	US-9455176-B2
Application number	US-201615072370-A
Country	US
Kind code	B2
Filing date	Mar 17, 2016
Priority date	Jan 21, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.

First claim

What is claimed is:

1. A manufacturing method for forming a semiconductor structure, comprising the following steps:
providing a substrate, having a plurality of dummy fin structures being disposed on the substrate, and a plurality of patterned hard masks being disposed on the plurality of dummy fin structures;
removing parts of the plurality of patterned hard masks disposed on the plurality of dummy fin structures;
performing an etching process to etch the substrate and the plurality of dummy fin structures simultaneously after said parts of the plurality of patterned hard masks are removed, and so as to simultaneously form at least one fin group and a plurality of sub-fin structures disposed in the substrate, wherein a top surface of each sub-fin structure of the plurality of sub-fin structures is lower than a top surface of the at least one fin group;
forming a liner covering and directly contacting each sub-fin structure of the plurality of sub-fin structures entirely, wherein the liner includes a recessed and protruding profile; and
forming a shallow trench isolation (STI) made of an insulating layer in the substrate, wherein the plurality of sub-fin structures are completely covered by the shallow trench isolation.

2. The method of claim 1 , wherein the process for removing said parts of the plurality of patterned hard masks comprises:
forming a patterned photoresist layer to cover parts of the plurality of dummy fin structures and parts of the plurality of patterned hard masks; and
performing an etching process, to remove the plurality of patterned hard masks that are not covered by the patterned photoresist layer.

3. The method of claim 1 , further comprising performing a planarization process after the insulating layer is formed on the at least one fin group and the plurality of sub-fin structures.

4. The method of claim 3 , further comprising performing an etching back process to the insulating layer, so as to expose parts of the at least one fin group.

5. The method of claim 3 , further comprising performing an anneal process to the insulating layer.

6. The method of claim 1 , wherein the at least one fin group is disposed between two sub-fin structures of the plurality of sub-fin structures.

7. The method of claim 1 , wherein each sub-fin structure of the plurality of sub-fin structures is a floating structure which is electrically isolated from a device.

8. The method of claim 1 , wherein the at least one fin group includes a plurality of main fin structures.

9. The method of claim 1 , wherein the method for forming the plurality of patterned hard mask comprises a sidewall image transfer process.

10. The method of claim 1 , further comprising performing an etching back process to remove parts of the STI and to remove parts of the liner, after the etching back process is performed, a top surface of the STI and a top surface of the liner are on a same level, and parts of the liner are exposed by the STI.

11. The method of claim 1 , wherein after said parts of the plurality of patterned hard masks are removed, the rest of the plurality of patterned hard masks is exposed during the etching process.

Assignees

• United Microelectronics Corp

Inventors

• Tsao Po-Chao
• Kuo Lung-En
• Lin Chien-Ting
• Tzou Shih-Fang

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title